I'm always getting a high impedance output in my Verilog Simulation!!!

[Alberto]

Hey all!

I've just started to learn Verilog at home having purchased a DE0 Nano Development Board with a Cyclone 4 Series FPGA on it. I'm in the upper sixth form (the year before uni in england) and thus have no teachers to ask questions too, so the only research I've done is what I can find out on my own. To get started I've tried to right some simple behavioral level code for a flip flop that will drive the LED's on the development board. Press one button and one LED lights, press the other the second LED lights and the first goes off, etc. Here's the code:

// This is the verilog code for a Flip Flop
// It's output will be connected up to one of the eight LED's on the DE0 nano dev board!
module flip_flop (
// Defining Internal module Variables
in_a,
in_b,
clock,
out_a,
out_b
);

// Input Ports
input in_a, in_b, clock;

// Output Ports
output out_a, out_b;

// Port Types
reg out_a, out_b;

// Main Behavioural Code
always @ (posedge clock)
if (in_a == 1'b0) begin
   if (out_a == 1'b0) begin
      out_a <= 1;
      out_b <= 1;
   end
end else if (in_b == 1'b0) begin
   if (out_b == 1'b0) begin
      out_a <= 0;
      out_b <= 1;
   end
end else begin
   out_a <= 1;
   out_b <= 0;
end

endmodule

// Test Bench Code begins here
module flip_flop_tb;

reg in_a, in_b, clock;
wire out_a, out_b;

initial begin
   $monitor ("in_a = %b, in_b = %b, out_a = %b, out_b = %b", in_a,in_b,out_a,out_b);
   clock = 0;
   in_a = 1;
   in_b = 1;
   #5 in_a = 0;
   #10 in_a = 1;
   #10 in_b = 0;
   #10 in_b = 1;
   #10 $finish;
end

always begin
   #5 clock = !clock;
end

endmodule

I put the test bench in the same file just to keep things simple. I am using the online system EDA playground to simulate the code as it keeps things simple. The code simulates and runs fine as far as I can tell, however when I look at the output levels after it has run they are always high impedance. Being new to verilog I have no idea what I'm doing wrong :S I've tried to compare it to an example to see what I might be doing wrong, but I just can't see it!

Thanks very much for the help in advance!

Alberto

[lincoln]

Because nothing is driving the signals. You have not instantiated you module to test in the test bench. In the test bench you have defined signals but they don't go any where.  add:

flip_flop uut ( .in_a(in_a),
                    .in_b(in_b),
                    .clock(clock),
                    .out_a(out_a),
                    .out_b(out_b)
);

This will create a flip_flop named uut and wire it up. Now, as far as your flop go, i'm not sure I see how it will behave as a flop but that is a different question. Also you can use @(posedge clk) in you test bench, like : @(posedge clk) in_b=1'b0; ect.

[Alberto]

Hey!

Sorry for the late reply on this! Got carried away with other things! Thanks so much for your help, that makes much more sense now. The testbench is a little bit confusing when you've never seen it before!

Thanks again,

Alberto!