Grounding of Crystal - Digital or Analog?

[ssashton]

Hi,

I'm making a board with a mixed signal DSP chip. Would it be best practice to ground the oscillator crystal to the digital ground plane or the analog?

I assume digital, but looking back at a past PCB I did years ago I have it going to analog ground and I have a strong feeling I might have tested it in practice to see what was best and this is counter-intuitive to me given the sharp waveform of the clock signal, but maybe it is especially low current and benefits from the cleaner ground??

Thoughts welcomed. Also welcome tips for schematic layout! Like Q1 blocking the MP pins. How would you handle that, use nets?

[RoGeorge]

I'll tie the oscillator to the analog ground:
https://www.analog.com/media/en/training-seminars/tutorials/MT-031.pdf

[pigrew]

I think it's likely using PGND (the pin right next to the crystal pins), though I don't see anything specifying either way. Perhaps you can download the layout of their evaluation board, and check how they do it?

You might be able to tell by using a multimeter "diode" function to see if there is a (single) ESD diode from the XTAL pins to the particular GND or VDD pins of the different power domains. The diode voltage should be higher (multiple diodes in series) to the other domains.

However, the datasheet notes:

A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.

If I were doing this design, I would use a single ground plane. Perhaps I would add a U-shaped cut-out of the ground plane around the crystal, to direct the GND return current towards the DSP.

[Doctorandus_P]

As far as I know using separate GND planes for analog and digital is deprecated, and a big GND plane for everything is used these days.
You do have to keep track of which signals go where, putting physical distance between high(er) frequencey & digital stuff and sensitive analog stuff is mandatory. With all high frequency stuff, the loop inductance is much more important then the length of the tracks, so carefully analyze the return path of each signal, and how it flows trough the GND plane.

Using short tracks for all hishspeed tracks does reduce emintted EMI and the ability to pickup noise. Each wire is both a sending and receiving antenna.

Crystals easily pick up noise from neaby tracks.
For the cleanest routing around your crystal, put it very close to the pins, and put it on a very small GND plane that is connected to the big GND plane only at the crystal pins of your DSP chip. This ensures that no currents flow thought the GND plane under the crystal (Except the crystal signals themselves) and also te crystal caps connect here to each other.

According to some, it's even better to just make a hole in the GND plane around the wires to the crystal. When there is no other copper, then there can also be no capacitive coupling.

[ssashton]

I'll tie the oscillator to the analog ground:
https://www.analog.com/media/en/training-seminars/tutorials/MT-031.pdf

That looks like a good read, thanks!

[ssashton]

I think it's likely using PGND (the pin right next to the crystal pins), though I don't see anything specifying either way. Perhaps you can download the layout of their evaluation board, and check how they do it?

You might be able to tell by using a multimeter "diode" function to see if there is a (single) ESD diode from the XTAL pins to the particular GND or VDD pins of the different power domains. The diode voltage should be higher (multiple diodes in series) to the other domains.

However, the datasheet notes:

A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.

If I were doing this design, I would use a single ground plane. Perhaps I would add a U-shaped cut-out of the ground plane around the crystal, to direct the GND return current towards the DSP.

Reading between the lines you are saying the important thing is not 'what's best practice' but rather where they have tied ground for the oscillator drive inside the chip?

The datasheet says a single ground plane can be used, but I don't think it will be optimal. I have a PCB like that from AliExpress and it has some noise. Certainly any input / output buffers and filtering will work best when nowhere near digital ground currents.

[wraper]

The best likely would be to not split the ground. As in most cases it does more harm than good.

[ssashton]

For the cleanest routing around your crystal, put it very close to the pins, and put it on a very small GND plane that is connected to the big GND plane only at the crystal pins of your DSP chip. This ensures that no currents flow thought the GND plane under the crystal (Except the crystal signals themselves) and also te crystal caps connect here to each other.

According to some, it's even better to just make a hole in the GND plane around the wires to the crystal. When there is no other copper, then there can also be no capacitive coupling.

I'm not sure I undertand your description. Could you draw a diagram or something, please?

[ssashton]

The best likely would be to not split the ground. As in most cases it does more harm than good.

I'll have to watch that later, but FWIW this is an audio frequency board in the analog domain. Ground impedance is everything, no HF effects to keep current near the signal traces.

[pigrew]

Reading between the lines you are saying the important thing is not 'what's best practice' but rather where they have tied ground for the oscillator drive inside the chip?

The datasheet says a single ground plane can be used, but I don't think it will be optimal. I have a PCB like that from AliExpress and it has some noise. Certainly any input / output buffers and filtering will work best when nowhere near digital ground currents.

Yes, I'm saying the most important thing is that there is a short return current path to the IC's crystal oscillator circuitry (refer to Doctorandus_P's post).

The IC has four power domains: IOVDD, VDD, VDDA, and VDDP. Inside the chip, there are likely antiparallel diodes between all of the GND domains, or perhaps they directly tie them together or use a resistor between domains.... Between voltage nets, there will be antiparallel series diodes (to account for the voltage differences between domains).

The critical factor is to reduce loop areas. If you tie the capacitors to the wrong GND pin, the return ground current will have to flow far away through the point of connection between the planes (or the capacitance across the IC's internal diodes or the decoupling capacitors you have populated). This would create a large loop, creating EMI/EMC issues.

I think your initial question should be rephrased as: Should the VDDP domain be tied to the digital or the analog plane? The modern answer is to use a single GND domain. My guess is you'll get better performance with it tied to the VDD/VDDIO GND plane versus the GNDA plane, but expect the single plane to be best.

Also keep in mind that the interconnection between GNDA and GNDD has to be under the DSP IC, and that all tracks going across domains have to cross in proximity to this interconnection.

For the cleanest routing around your crystal, put it very close to the pins, and put it on a very small GND plane that is connected to the big GND plane only at the crystal pins of your DSP chip. This ensures that no currents flow thought the GND plane under the crystal (Except the crystal signals themselves) and also te crystal caps connect here to each other.

According to some, it's even better to just make a hole in the GND plane around the wires to the crystal. When there is no other copper, then there can also be no capacitive coupling.

I'm not sure I undertand your description. Could you draw a diagram or something, please?

Look at TI application note SLAA322B figure 7. You use an isolated GND plane under the crystal & capacitors.

The best likely would be to not split the ground. As in most cases it does more harm than good.

I'll have to watch that later, but FWIW this is an audio frequency board in the analog domain. Ground impedance is everything, no HF effects to keep current near the signal traces.

In this case, it's a sigma-delta/delta-sigma ADC&DAC. They'll operate at many MHz, and are in the analog power domain.

[pigrew]

In order to make the schematic cleaner, I would edit the DSP's symbol so that the pins are logically grouped together (like how it is in the datasheet), instead of being based on the physical positions, or even split it up into multiple "units" (one for power, one for signals). Check the datasheet's schematics for an example of what I'm suggesting.

Did you make a mistake with pins 19 and 20? Perhaps they should be grounded? I'm not sure...

So... what's your proposed board stackup? 4-layer? 6-layer? In the case of 4-layer, you might want to tie both inner planes to GND, or consider a split Vdd plane on L3 if you can segregate your tracks appropriately. (Signals should only be routed on top of their respective GND or power plane). Though since you are using 3.3V for nearly every signal, signal/GND/3.3V/signal could work. Routing might also work out if you split the VDD plane into analog and digital halves.

I found a post with some suggestions about PCB design for the DSP for reducing noise.

[ssashton]

Oh good find on the layout thread!

Pin 20 can trigger an eeprom write to save settings when a falling voltage is detected. Connecting it to a pulled high GPIO (pin 19) seemed like a way to do that, while also letting me trigger any time I like, such as a gain level is changed.

[ssashton]

Changing the topic - I will run my op-amps from a single rail so use a mid-rail bias. Would there likely be a cross-talk benefit to using a dedicated bias supply for each channel on inputs and outputs?

Current arrangement looks like this for inputs  and same bias supply used on the output channels as well.
(Ignore the different ground symbols).

[LittleRain]

It may be a good idea to just have a shared ground plane (on both sides).
Proper grounding is very important and is the main reason 2 layer PCBs have much more EMI than a multi-layer PCB.
When splitting ground plane, if not done properly it will cause a lot more problems than if you just combined the 2.

Here is an article to read, and if you do decide to separate them, there is good info here on how to avoid causing more EMI issues.
https://www.nwengineeringllc.com/article/should-you-split-ground-planes-in-mixed-signal-pcb-design.php

[ssashton]

I see a lot of talk about radiated emissions and EMC testing when discussing ground planes. However I am primarily interested in signal integrity. This PCB will be for audio signals so my main concern is minimising the signal noise floor.

Is achieving both of these goals actually the same thing, or would there be differences in ground layout for these priorities?

EDIT: My 'like' of split grounds comes from experience with high and low current parts on the same PCB, not with digital. I recall a audio frequency power amp design that used a single ground plane and the return currents from the load massively interfered with the low level signals on the PCB. Separating the low and high current ground areas and returning them by traces to the smoothing cap helped massively.

Should high and low current (but all low frequency) stuff like this also still be a single ground plane and my error might have been in other layout details?

[ssashton]

Today I started on the layout. Before I get too far, can I get some feedback please? This will be 4 layer with a single ground plane.

Forgive the crude drawing:

[LittleRain]

I'm definitely not a professional PCB designer. Everything I know is from what I've read/watched online, and all the circuits (mostly digital) I've made.

All I can say is that I don't see any reasons your layout would cause a problem, I do think having the power connector in the middle of digital and analog is a good idea.

Looks good to me, but I could be missing something obvious.

[pigrew]

Today I started on the layout. Before I get too far, can I get some feedback please? This will be 4 layer with a single ground plane.

Forgive the crude drawing:

You layout looks reasonable to me. Segregating the analog and digital is good, as is putting the switching regulator far away from the sensitive analog circuit.

Locating mounting holes and such would be the next step. The board is so long and skinny, that it likely would need >=5 mounting holes in order to prevent flex.

You may want to add a little bit of capacitance+resistance+TVS diodes near the audio input for ESD protection (and/or go overboard and place common mode chokes/ferrite beads..).

Are you using bipolar power supply? If so, I'd lean towards a SIGNAL,GND,GND,POWER layers.

If you are using a split rail, I would think about using SIGNAL,split-bias,GND,power (I'm actually not sure if that's a good idea, but maybe?).

Assuming all of your digital signals are in the 3.3V domain (I can't remember), I may use power+SIGNAL,GND,3V3,signal for the digital side.  SIGNAL/power-GND-GND-signal/power is always an option, too.

[ssashton]

I have a single +15V rail, but all on-board parts have regulators.

Does this make sense?



I have power input to op-amp U6 (that generates a mid-rail bias for other parts). The power traces goes first to C52 then to U6. U6 gnd pin returns first to C52 then to the gnd plane.

The output of U6 (bias voltage) goes first to C53 then to other components. C53 returns first to U6 gnd pin >> then to C53 and gnd plane.

Or should C53 return to the gnd plane or C52 first?

[pigrew]

Or should C53 return to the gnd plane or C52 first?

The literature I've read suggests always going to the decoupling capacitor, and then the power via.

The GND should either go straight to the GND plane, or to an immediately adjacent decoupling cap GND pad, and then to the via.

Having a via directly to the GND plane (and multiple vias) is lower inductance than having the long track to the decoupling capacitor.

One rule I use is to have >=1 GND via next to every GND pad of every component on the PCB (unless there's some contraindication, e.g. an immediately adjacent decoupling capacitor GND pad).

Having a star-ground or separate ground lines could be useful for minimizing ground bounce/DC offsets, but I figure it would make things worse in this design.

To really know, you'd need to do EM simulations....

[ssashton]

So you're saying do not bother returning the op-amp gnd pin directly to C52 and just use the gnd plane?

I did that becasue it is what was recommended for the DSP chip - but that does have adjacent power and gnd pins.

[pigrew]

So you're saying do not bother returning the op-amp gnd pin directly to C52 and just use the gnd plane?

I did that becasue it is what was recommended for the DSP chip - but that does have adjacent power and gnd pins.

Correct, I would use separate ground vias.

With the presented layout, any ground current (flowing out of pin 4) will cause a voltage rise on your GND pin there, which will then be coupled through C53 onto your output. Since the GND layer is much lower impedance, the pin8 current will cause less ground bounce on your C53 negative terminal.

Looking again, do verify that your op-amp is stable with a capacitive load in unity gain configuration (many are not).

Then again... I don't know how much of a real-world effect these layout tweaks would have.

[ssashton]

Thanks for all the help!

I'm actually thinking I might make a couple boards with a single ground plane and a couple with my usual method of local ground 'islands' that I trace back manually to the bulk cap. Then we can see what measurable differences I can find.

Actually In my older similar board (2 layer) I did not have any cap on the output of the bias op-amp. Although it is connected to many caps and resistors it is providing bias for (but bias will be on both sides of those components so no current).

I'll keep it in and try to remeber I might need to remove it when I come tessting.

[ssashton]

I've posted the full design schematic and layout here and would really appreciate feedback

https://www.eevblog.com/forum/projects/can-i-get-some-feedback-please/