The problem with your circuit is that that particular version of a JK flop is edge triggered and the trigger pulse must be shorter than the propagation through the ring-tailed NAND gates.
This is not an edge triggered JK flop. It is a latch. If it were edge triggered and done with simple combinational logic elements, you'd see two RS latches in series with surrounding logic.
Here's another explanation.
The right half of the circuit is a simple RS latch with an R input (that resets the latch when it is low) and an S input (that sets the latch when it is low). These are "active low" inputs to the cross coupled latch -- consider the R or S input to be true (do the action) when the level at the input is LOW. The Q output is oposite the S input and the !Q output is opposite the R input.
Remember: when S is true, Q becomes true and !Q becomes false. When R is true, Q becomes false and !Q becomes true. When neither R or S is true, Q and !Q are unchanged. If both R and S are true at the same time, Q and !Q will become true until R and S become false, at which case it is a bit of a carp shoot as to the final state.
The RS inputs are fed by two NAND gates. These can also be considered AND gates that produce an active low output -- TRUE when low, FALSE when high.
So, now let's write the equations for R and S.
S = J AND !Q AND CLOCK
R = K AND Q AND CLOCK
Note that when CLOCK is high, S or R can change at any time. This is what makes this a not-edge-triggered device. It is what the pros call a "latch" or "level sensitive".
When J and K are both true (high) and the clock is high, this widget is likely to be unstable. A true JK latch or flop should toggle the output when both J and K are true.
However, with a latch, any transition that results in
both J and K being true while the latch is "open" (in this case, when the clock input is HIGH) will leave the latch in an uncertain state.
JK elements, when they are in cell libraries or parts catalogs at all, are typically edge triggered. But, as I said, this one is not.
If you want to simulate your circuit, cut down the pulse width or couple it through a small capacitor with the input tied to ground through a resistor - make a differentiator ahead of the clock input to the chip. I don't know if I would bother with the negative spike or whether I might run the differentiated square wave through a diode to eliminate the negative spikes.
Perhaps that will help in a simulator, but it is absolutely not a good idea (TM) in any actual logic. This "use a cap" to get an edge was used in the 60s with discrete devices, and every now and then today when you want some kind of delay (like a reset signal) but in these cases the RC circuit should always drive a schmitt trigger. Others may use caps in the signal line in a feedback type oscillator, using logic gates and a resonator, though that too has been supplanted in professional practice.
When I see a capacitor in a logic circuit (that is, in line or across a logic signal) it is either for DC isolation on a high speed (f'rinstance SERDES) channel, or a sign that the designer was lost.
I'm not sure why this circuit did not simulate correctly. What simulator are you using?
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