I'm not clear on what the inner transistors Q1 and Q3 are doing -- you can ground those bases and it still works (the two 50 Ohm resistors form a virtual ground), but if you remove Q1 and Q3 the doubled output amplitude drops significantly. Some sort of VBE compensation?
We used this on many of the RF/MW SoC chips we did back starting in ~2000 as a Square-Law Detector for accurate on-chip RF signal measurements, then a little later as a frequency doubler and also used as a real-time analog signal conditioner where the output current closely approximated a hyperbolic-trigonometeric function (likely the Cosh function) to "equalize" a dynamic signal in real time.
It's been too long and I'm too old remember the finer details and too lazy to do the math

I'm sure one could reverse engineer this and produce the non-linear transfer function finer details if necessary.
Do recall the two center transistors were for compensation and vaguely remember the 4 transistors were located in an Erdi Quad arrangement for temperature and process gradient compensation. Q2 and Q4 did have series resistors to the bases (not shown in first schematic, but redone below with resistors) so the arrangement had all 4 transistors "seeing" similar source impedances, altho none were exactly 50 ohms. This of course made the differential output current almost zero without an input signal, which was a necessary requirement.
Anyway, hope this helps, altho don't feel the OP deserves any help from anyone with the attitude shown, and why we didn't show the schematic earlier.
Edit: Added a couple plots showing Differential Output Current vs. Differential Input Voltage. Fist plot is with Vsource +-20mV and second plot is with Vsource +-200mv. Note, input sources V3 and V4 include 50 ohm impedances.
Best,