Material type for power supply decoupling capacitors

[matrixofdynamism]

I am trying to understand the correct way to choose decoupling capacitors. What I know is that for modern devices we should choose two or three values. These will work together to form a impedance-frequency profile with few peaks where the low frequency and high frequency noise are both going to be filtered. The peaks are formed since each capacitor has ESL which becomes dominant at high frequencies. This cannot be avoided.

The subject here is decoupling capacitors for FPGA, CPLD and processors. From what I know, we need to use electrolytic capacitor at short distance from power pins which would be several uF or even a few 10suF. Then we need ceramic capacitors that are supposed to be very very close to the power supply pins and must have very short connections to the ground to minimize inductance of the power-ground loop. This is because the wavelength of the noise means that the ceramic capacitors must be close to the power pin to be effective.

The thing is that electrolytic capacitors and ceramic capacitors come in different packages and material types. The dielectric affects the ESL and ESR of the capacitors. So, do we try to buy special type capacitors like the Low Inductance Chip Capacitor (LICC) or just a plain multilayer ceramic capacitors (MLCC) will do? What about the package size, do we go for the smallest that the PCB assembly house can assemble? What about tantalum capacitors? Are these ones supposed to be avoided since they have larger ESR compared with the other types? There are so many other capacitor types like Mica, Metal Film e.t.c.

[RoGeorge]

Usually the FPGA manufacturer provides this info in their datasheets and/or application notes, plus a typical PCB layout for each type of FPGA package.

[matrixofdynamism]

I am trying to learn the theory and there appear to be different pieces of information that say different things. Basically what I am trying to understand is that, since we all these different type of capacitor types, which ones are used in power supply decoupling and why?

Ceramic
Electrolytic
Tantalum
Mica
Metal film

Is using only Ceramic capacitor not enough?

[Siwastaja]

I am trying to understand the correct way to choose decoupling capacitors. What I know is that for modern devices we should choose two or three values. These will work together to form a impedance-frequency profile with few peaks where the low frequency and high frequency noise are both going to be filtered.

No, no, no and again no! This is a total bullshit myth. Don't buy it. For explanation, read this thread and the links posted carefully: https://www.eevblog.com/forum/projects/decoupling-caps-value/?all

[Vovk_Z]

Ceramic
Electrolytic
Tantalum
Mica
Metal film

There are more types. I can add at least several different types more:
Ceramics Class 1, Ceramics Class 2, Wet Electrolytic, Solid Electrolyte, and several different types of films with different properties (obsolete and not obsolete).
What properties do we want from caps? There are a lot different properties to consider (I'm talking not about decoupling but about other functions too). They could be: just simple high capacitanse (e.g. for low frequency rectifiers), low ESR and high ripple current (SMPS output), low ESL for high frequency circuits, capacitance stability for frequency-dependent circuits: temperature stability, age stability, voltage stability, ... other types of stability (e.g. Dielectric absorption vital for accurate instrumentation etc), mechanical stability (parasitic pieso effects), etc.

[Siwastaja]

I am trying to learn the theory and there appear to be different pieces of information that say different things. Basically what I am trying to understand is that, since we all these different type of capacitor types, which ones are used in power supply decoupling and why?

Ceramic
Electrolytic
Tantalum
Mica
Metal film

Is using only Ceramic capacitor not enough?

Ceramic (MLCC) for all low voltage (say <100V) bypassing, one value per voltage rail, biggest possible C in smallest possible physical case for smallest possible ESL. In other words, usually the target is lowest possible impedance at some relatively high frequency, which drives you to certain maximum L (say 5-10nH), which drives you in a certain package size (say 0603 max or more preferably 0402). Then you can pick largest C available in that package, more C keeps the HF impedance the same but improves over low frequency impedance.

MLCC ESR is near-zero which causes a risk of ringing if input voltage is suddenly applied (e.g. hotplug, mechanical switch, wire inductance). This is damped by adding high-ESR capacitance in parallel, so that C of this high-ESR is significantly more, for example if you have 20µF of MLCC you could use 100µF of electrolytic. The two usual high-ESR capacitor types are the good old cheap aluminum electrolytic capacitors, and tantalums.

Some old or otherwise special snowflake regulators, voltage references etc. are only stable if they have high enough ESR at their outputs. This is another reason to add high-ESR in parallel with the usual MLCC-bypassed distribution network.

Reason to use tantalum over aluminum electrolytic is more stable (against aging, temperature, unit-to-unit variation) and well-specified ESR value (also capacitance). Otherwise than that, both aluminum electrolytics and tantalum offer high enough ESR to basically always self-stabilize the network (i.e., not oscillate with parasitic inductances like MLCCs do).

Explicit series resistors with MLCCs are always an option and work fine, too, but if you need a lot of capacitance say 100µF, an electrolytic is significantly cheaper and takes smaller board area compared to MLCC + resistor banks.

[Solder_Junkie]

It helps to measure, rather than guessing, or even taking notice of old publications.

I have been surprised at how effective small aluminium electrolytic caps are at decoupling HF signals in the 2 to 30 MHz region. The books will tell you to use multilayer ceramic of around 100 nF, yet a 33 uF electrolytic had less measured HF signal across it! This was an 8 MHz crystal oscillator supply measured with a 100 MHz scope.

Another point, not often considered, is the capacitance of an electrolytic capacitor may be less than indicated on the can if it has a Voltage rating much in excess of the Voltage across it.

Nothing is simple in electronics.

SJ

[Siwastaja]

I have been surprised at how effective small aluminium electrolytic caps are at decoupling HF signals in the 2 to 30 MHz region. The books will tell you to use multilayer ceramic of around 100 nF, yet a 33 uF electrolytic had less measured HF signal across it! This was an 8 MHz crystal oscillator supply measured with a 100 MHz scope.

The issue with 33uF electrolytic is in ESR + ESL. ESR alone will be several ohms, so that limits the available HF impedance. Then there is ESL; because the 33uF part is larger, there will be longer distance from your load, trough the PCB, through the legs, to the closest layers of foil inside the capacitor. Maybe 20nH worth. But if you compared with a 100nF ceramic placed equally far away, then it has the same ESL! The idea with the 100nF MLCC is that it's available in 0402, even 0201 size, and you can place it closer to the load, for maybe 5nH. But if 20nH was enough to begin with, then you won't see a difference.

And what even is "HF"? Maybe you are talking about relatively low frequencies where 100nF has too much impedance simply because of too little C. This is why it's best for low voltages (<10V), by far, to use something like 1uF because it's still available in small enough packages so high-frequency side is optimal, yet the low frequency side bypassing extends 10 times further than with the 100nF part.

[matrixofdynamism]

There is this one issue related with capacitors. We like to have as low ESL as possible, ok clear.

Now coming to ESR, is ESR a good thing or a bad thing in capacitors? Capacitor is supposed to have only the ideal capacitor characteristic so having ESR seems more like a parasitic affect. I have found that having some ESR is required in output capacitor for a linear voltage regulator called LM1117 and thus we use tantalum capacitor rather than ceramic.

Other than this, I know that ceramic capacitors (atleast the Class I) are the closest we have to the ideal capacitor. The other ones like electrolytic and tantalum have a lot of stuff going on in their physics and chemistry that makes them less closer to the ideal capacitor, one of these things is the ESR.

[T3sl4co1l]

ESR needs to be low enough for the application, and then whether it should be lower or not depends on the network design.

Notice the power supply is a network (PDN, power distribution network).  There is some noise and ripple introduced to this network, by power supplies, loads switching on and off and buzzing at various frequencies, etc.; and every load needs to see, at most, some maximum impedance, lest its PSRR give insufficient performance for the overall system, or it ceases to function at all (digital logic can be interrupted by sudden changes in supply, corrupting logic operations, or program flow; it doesn't matter if the change was caused by itself (change in current draw) or externally).

Electrolytics are often chosen for modest ESR in parallel with a smaller ceramic, so that impedance is low at high frequencies, but the impedance doesn't increase too quickly at middle frequencies where the ceramic would otherwise resonate with connected inductances.  If intentional inductance is added (say for local filtering of, I don't know, an analog section, ADC, PLL, etc.), additional resistance might be needed to ensure it's well damped at the crossover frequency.

Note that trace and even component inductances matter, since we're talking such low ESRs in ceramic caps.  This is a bit annoying at times; in a recent LLC resonant power supply design, I tested an array of 3 x 10nF C0G in parallel, which exhibited a parasitic resonant mode (a "see-saw" mode where the two end capacitors alternate around the midpoint).  The voltage amplitude was small enough not to be an EMI concern, but it was definitely a dynamic behavior of the system, as evidenced from inductive probe measurements (i.e. I sensed the current flowing between the two end caps).  1210 C0Gs in parallel is about, what, 4nH inductance between neighbors?  So ballpark Zo = sqrt(4nH/10nF) = 0.63 ohms, quite a bit higher than the 10s mΩ ESR these capacitors have at that frequency.  Hence the ringing waveform, rather than a damped response.

Type 2 capacitors, you have up to a modest distance between them (roughly, a few body lengths, maybe?), where the resonant mode is damped (inductance low enough that ESR dominates) and, basically, they look like they're acting in parallel.  For example, a typical 10uF 1206 might have 8mΩ ESR and 2.5nH, for a total (around the loop between an adjacent pair) of 5uF, 16mΩ and 5nH; this gives a resonant impedance of 32mΩ and a Q factor of 2 -- not well damped, but low enough you might not notice.  In particular, the resulting impedance peak is Q Zo or 64mΩ, still pretty low.

Whether this is low enough, depends on the load.  Consider a CPU that's ticking on and off as it goes through tasks; when it gets going, maybe it draws 1A at 3.3V, and near zero otherwise.  Say the supply needs to stay within 5%, or a peak AC ripple of 165mV.  That defines the maximum supply impedance: a peak change of 165mV from a step change of 1A is 165mΩ.  The risetime is on the order of a few tens of nanoseconds, so the impedance needs to be within this range up to 50 or 100MHz*.  So we need ESR at most this amount, but also enough capacitors dotted around that the total supply inductance (to the chip, or at least to its pins/pads) is under 0.5nH.  And preferably a lot less, since that's assuming the resistor and inductor voltage drops are independent, which will never be the case (the real value is their vector sum).

So we might dot a bunch of 0402 chips around such an IC, and supply it through a power plane (low inductance), with some aluminum polymer caps nearby (selected for modest ESR, say 30-100mΩ; polymers have generally low ESR but are available in a wide range, so this selection is feasible) to help dampen the plane inductance, or the inductance between small caps.

*Such CPUs are normally constructed on interposers, with local bypass near the chip; I won't go into detail here, but following the same reasoning, it's basically impossible to treat frequencies higher than this, to such low impedances, at the PCB level, and this is basically why they require onboard capacitors.

Tim

[Siwastaja]

Now coming to ESR, is ESR a good thing or a bad thing in capacitors? Capacitor is supposed to have only the ideal capacitor characteristic so having ESR seems more like a parasitic affect. I have found that having some ESR is required in output capacitor for a linear voltage regulator called LM1117 and thus we use tantalum capacitor rather than ceramic.

ESR has good and bad sides to it. The obvious bad sides are, the capacitor is not going to filter as well as it could, i.e., current ripple dI results in voltage ripple dV = ESR*dI even if you make C infinite. Then there are I^2*R losses which can be significant in things like buck converter input capacitors. (This is how electrolytic capacitors overheat and dry up in motherboards.)

Positive is that energy loss is sometimes useful for damping, this is exactly what shock absorbers in car suspension do, they convert mechanical energy to heat (car body weight being C, and springs being L), to stop back-and-forth energy transfer (peaking) at some resonant frequency. What comes to 1117 though, it's tragedic you have to add loss to compensate for the crappy control loop, because in $((2011+11+1)), way better regulators exist which are perfectly stable with any MLCC with near-zero ESR. So there is no fundamental physical reason you need ESR at regulator output, just certain (mostly old) parts affected by limits of their engineering.

But even if you replace crappy regulator control loops with modern, decent ones, some passive power distribution networks might still oscillate, most typically long DC input wires combined with a lot of on-board capacitance, so that power is applied by hot-plugging a connector or through a mechanical switch (or fast-switching transistor). The solution is to add an electrolytic cap. See https://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf  But judging by number of capacitors, in 99.99% of cases you really want minimum possible ESR.

[matrixofdynamism]

I see, it seems that topic of PDN is basically as crazy as anything in analogue electronics once we deep dive. Most things in analogue electronics that I have seen so far are about using models and approximations that get us very close to the real answer with a small acceptable error (I am FPGA/ASIC design/verification person by the way). Now the reason all this PDN science appears so complicated is that, each case is unique and we are trying to optimize the final solution rather than aim for "good enough". The simplest reason is that the components today work at low voltage and can only tolerate very small ripple and might be taking a massive huge amount of current at very high switching speeds (for larger devices like high end FPGAs for example) thus "good enough" cannot be reached by using simple approximations.

I have learnt today that (a real) capacitor is basically an RLC network and this means that it has a resonance frequency and the R affects the damping. Depending on the R value the response could be under-damped, critically damped and over-damped. This implies that when a step voltage is applied across this network, it shall exhibit oscillation and this is what is not acceptable.

OK next question is, there was a time when it was recommended that we use 3 different value capacitors, one being electrolytic and the other two being ceramic. However, this is not considered old rule that was followed blindly and is not applicable to modern devices. Now, if we use (atleast) two different valued capacitors, we shall see a peak in the impedance profile of the PDN. If we use two of the same capacitor value then the impedance profile will shift downwards i.e the resonance point will move to a smaller impedance value. The question is, is it not better to use multiple values so we cover a larger frequency range rather than multiple capacitors of the same value?

[Siwastaja]

Yeah. Most important is to recognize wrong and dangerous "rules of thumb" which usually make the design perform worse, usually significantly so, and only in some weird rare corner cases give modest improvements. These are:

* Different values and sizes of MLCCs in same power rail,
* Power planes providing magical super capacitance everywhere without need of local bypassing
* Splits in ground planes, or multiple ground nets connected together somewhere, somehow

Once you ignore this stuff, your life suddenly becomes much more easier. A few useful rules of thumb:

* Add an electrolytic bulk capacitor in parallel with board input power (because that comes from inductive wiring with possibility of hotplug)
* Always try to use regulators and references which are stable with MLCC output capacitors
* Use largest possible capacitance in smallest possible package everywhere for local bypassing. Realistically this often means you buy reels of 0402 1uF. Only use that one size per rail. If you for some reason need 2uF on a pin, put two in parallel there.
* Don't skimp on ground stiching vias, vias are free or nearly free of charge
* With good local bypassing, power rails can be just thick tracks, or polygon pours that conform to each other in a single layer.

[Infraviolet]

Reply #5, "This is damped by adding high-ESR capacitance in parallel"

Just to note, if your sizing requirements make fitting an electrolytic bothersome, or if you favour ceramics because they last virtually forever whereas elecrolytics often have a predicted lifespan of use, you can use a ceramic in series with a few ohms to tens of ohms of resistance to simulate a high-ESR capacitor and put this pair in parallel with your other ceramic caps so as to smooth off and slow down any spikes during hot-plugging power-on events. I had a circuit board with lots of 10u 0603 ceramic caps on it at the end of some 30cm wires (length adds inductance to cause LC switch-on spikes) which normlly spiked for a fraction of a microsecond to 8 volts when being hot plugged to a 5V supply. With a 10u in series with 1.5 ohms put in parallel to this the spikes were kept below 5.7V.

[T3sl4co1l]

Yeah. Most important is to recognize wrong and dangerous "rules of thumb" which usually make the design perform worse, usually significantly so, and only in some weird rare corner cases give modest improvements. These are:

* Different values and sizes of MLCCs in same power rail,
* Power planes providing magical super capacitance everywhere without need of local bypassing
* Splits in ground planes, or multiple ground nets connected together somewhere, somehow

Once you ignore this stuff, your life suddenly becomes much more easier.

And, be careful to note in which ways these are still useful, and how the thumb-rules [mis]apply.

Different size/value capacitors fail because of the relative values of ESR and ESL.  Probably this was never a great idea (ESR isn't higher for disc types, is it? Maybe a little, for Z5U or Y5P?)  It's indeed a fine approach, if you have a modest amount of ESR available; but using just ceramics, you don't, and it's bad advice.  And you still want to use mostly ceramics, so you need to be very judicious in where and when you place the ESR-ey capacitors.

Power planes -- have very little capacitance compared to even a single chip.  Even an 8-layer board might only have 10s of nF, and a typical regional pour (under a local IC and related components) might be 100s pF.  Indeed the small capacitance and low ESR and ESL can make problems where it resonates with the bypass ESLs, at the highest frequencies (2nH and 1nF is 112MHz).  Their primary value is exactly that, the low ESL.  A solid plane looks like a nearly ideal connection between points, with mainly inductance local to the region around each via (plus via and trace/component inductance as usual).  (That is, consider a coaxial cylinder where the center conductor (radius r) is the via, the length of the cylinder is the height between planes h, and suppose the planes are shorted at some distance R related to the distance between neighboring bypasses; we then have L ~ mu_0 h ln(R/r).  Since ln increases only gradually with large ratios, we can take this as a flat, say, couple nH per via, with the amount reduced when groups of vias are used in parallel, and when other bypasses are nearby.)

Split planes, are a nightmare and should be expunged from appnotes.  They are an important technique, but one that is extremely likely to be misapplied by anyone but experts (and even then, an expert might be making merely an educated guess, and may suggest making several variants and testing each).  It's something of a last resort option, when all other methods have been exhausted.  What should be promoted, is separation of current loops: typically for an ADC for example, the dirty digital signals are on one side -- and their current flows and image currents (complementary current reflected in the ground plane) are similarly confined -- and the quiet analog signals are on the other side.  Just do this everywhere on the board and you significantly reduce crosstalk, interference, ground loop, etc.

A few useful rules of thumb:

* Add an electrolytic bulk capacitor in parallel with board input power (because that comes from inductive wiring with possibility of hotplug)
* Always try to use regulators and references which are stable with MLCC output capacitors
* Use largest possible capacitance in smallest possible package everywhere for local bypassing. Realistically this often means you buy reels of 0402 1uF. Only use that one size per rail. If you for some reason need 2uF on a pin, put two in parallel there.
* Don't skimp on ground stiching vias, vias are free or nearly free of charge
* With good local bypassing, power rails can be just thick tracks, or polygon pours that conform to each other in a single layer.

Hotplug can also be solved with a TVS (which also handles other kinds of surge, of course; not that that's usually any concern in a power adapter input situation); but the electrolytic provides dynamic damping of course, not just for inrush but for operation in general.

Large value capacitors aren't really all that important, I would say; even 10s nF are adequate for most IC bypassing purposes.  And large values in small chips have the downside of a significant C(V) curve, even at just a couple volts.  (Which, mind, is far from a show stopper: even if it's -70% at 5V, that's still plenty of capacitance left.  Nonlinear parts aren't automatically bad, they just need more careful consideration.)

I use 100nF, strictly out of habit.  Bypasses are one of those things that's either so loosely defined as to be nearly impossible to justify, or that's a starting point i.e. assumed conditions, or a postulate if you will, and the number and distribution of them matters more than any particular value.

The upside to large values is, you can just pile up a bunch more where you do need the extra value. Maybe save on some 22uF ceramics or whatever because you've already got as much spread across the plane!

Ground stitching -- this has been discussed to death in various places; search for a few of my posts here on the topic.

I would still recommend planes over power traces, for multilayer -- but if the assumption is 2-layer, absolutely, pour grounds route everything else, and stitch ground liberally around those routes.  (Ah, actually, that must've been what you were talking about, Siwastaja?)

For FPGA stuff, you'll probably have a hard time getting away with 2 layers (maybe the smallest ones), and 4 is very minimal for anything bigger than a TQFP.

Reply #5, "This is damped by adding high-ESR capacitance in parallel"

Just to note, if your sizing requirements make fitting an electrolytic bothersome, or if you favour ceramics because they last virtually forever whereas elecrolytics often have a predicted lifespan of use, you can use a ceramic in series with a few ohms to tens of ohms of resistance to simulate a high-ESR capacitor and put this pair in parallel with your other ceramic caps so as to smooth off and slow down any spikes during hot-plugging power-on events. I had a circuit board with lots of 10u 0603 ceramic caps on it at the end of some 30cm wires (length adds inductance to cause LC switch-on spikes) which normlly spiked for a fraction of a microsecond to 8 volts when being hot plugged to a 5V supply. With a 10u in series with 1.5 ohms put in parallel to this the spikes were kept below 5.7V.

Note that external resistors have ESL too, so you can end up not getting the damping effect you might've thought; especially for low values like 10s-100s mΩ.  Use small, wide-format resistors (and capacitors), or multiple in parallel (which again, can be distributed around when it's a parallel plane or supply connection).

Tim

[jmw]

I recently built a setup for testing PDNs along with a test board that allows me to mockup a mix of capacitors in different placements and measure them. I wrote a blog/article here, you may find it useful: https://jmw.name/projects/exploring-pdns/ Many of the topics in your original post are explored.

Specifically for FPGA decoupling, you really should check and follow the manufacturer recommendations. They have multiple power rails with different requirements. In particular, I remember Xilinx has very detailed recommendations, even including tests of different via routing styles

Component manufacturers have started making better web simulation tools available. I've found KEMET's K-Sim to be pretty handy: https://ksim3.kemet.com/capacitor-simulation, especially for prototyping with their tantalum capacitors because tantalums usually cite a headline ESR figure that is given for one frequency, but you need to know it behaves across a range of frequencies. For example https://www.kemet.com/en/us/capacitors/ceramic/product/T491A106K016AH.html: this part is a 10 µF 16 V tantalum that is rated at 3 Ω ESR, but the chart tells a different story for typical performance.

K-Sim is also good for developing an intuition about how to use ESR. If you play around with that tool, you'll notice that when you parallel two MLCC you will often get sharp resonant peaks in the impedance profile. Anytime you see two impedance graphs closing toward each other at 40 dB/decade (+20 dB/decade when ESL dominates minus -20 dB/decade when capacitance dominates = 40 dB/decade rate of closure), you will get resonant peaks. When you use a bulk capacitor with some ESR, the impedance graph has a flatter bottom, and the closure rate with a paralleled MLCC is around 20 dB/decade, which leads to a smooth single-pole rolloff.

[T3sl4co1l]

I recently built a setup for testing PDNs along with a test board that allows me to mockup a mix of capacitors in different placements and measure them. I wrote a blog/article here, you may find it useful: https://jmw.name/projects/exploring-pdns/ Many of the topics in your original post are explored.

Hm, just one end, not transfer too (connector at far end)?

Even here, be careful what to generalize from the measurements -- for example:

From the charts, it’s clear that capacitor placement matters much more on the two-layer board. Even 10 mm away, the frequency range where the capacitor impedance is less than 1 Ω has vastly shrunk. The four-layer board also shows this effect, but a .1 µF capacitor placed 10 mm away is nearly just as effective.

That's 10mm away at that trace width -- which is quite wide, so has considerable impact.  (This is covered a bit further down, where the trace is treated as a pour; it's just not emphasized here.)  Wide traces (\$w \gg h\$) are essentially L = \$\frac{\mu_0 l h}{w}\$ so the, what was that, about 4mm wide trace?, is equivalent to only 1mm of average-width (0.5mm) trace.  Though there are two gotchas with this estimate as well:
1. End effect.  Current is spreading out around the connections, making the trace effectively narrower near connections.  See my discussion of vias earlier; current is spreading out into parallel planes in a cylindrical area around the via.  The same applies here when the trace is wide (it looks more like a pour, locally, including this spreading effect).
2. A 0.5mm width trace is probably not "wide" anymore, and will have somewhat lower impedance than you would expect just from its rectangular dimensions.  That is, the fact that fields fringe out around its edges, basically give it more cross-section -- extending out sideways, not just underneath the trace.

So, even in an explanation, I have to be very careful about how I'm approximating things.  Have y'all noticed yet that these things are easier to just simulate, and not have to draw generalizations from?


A small clarification --

[type II capacitors are] anything that is not C0G/NP0 temperature coefficient

C0G are the most common type I, but not the only; AFAIK, all the design-tempco types are also free from C(V) effect.

You probably wouldn't have reason to use the others for PSU purposes, but B and SL types show up from time to time, and they're worth including in queries.


Also note in this,



(link if it doesn't embed: https://jmw.name/images/pdn/100nF+100uF_distance_2layer.svg )

there is clear peaking; if this were repeated with a range of ESRs, the peak impedance will fall as R approaches Zo (about 500mΩ).  If ESR were higher (1 or 2Ω and up), the peak would be below the ESR flat-band (to the left), which is certainly well damped, but yeah, then the ESR itself becomes dominant (in this case, over about the < 4MHz range).

Again, as I discussed above, the peak isn't necessarily a problem; as long as the peak impedance is below that required for the device(s) in question being bypassed, it's fine.

Overall good article!

Tim

[jmw]

Hm, just one end, not transfer too (connector at far end)?

From the first diagram on the page, ideally the ports are on top of each other
Anything else means there is unwanted inductance or transmission line discontinuity between the ports and the test network.

Just to clarify the linked chart, the purpose is make an indirect measurement via seeing a resonant frequency shift, since my spectrum analyzer can't go low enough to directly observe the response at frequencies where a 100 µF tantalum looks capacitive.

The rest: yes, especially on the 2-layer part the trace width means the PDN is not totally representative of a VCC net that is routed point-to-point with narrower traces. The board is more a playground to mockup capacitor networks for quick & easy comparison. Someday I need to try making a clone of the Picotest probes for measuring boards in situ...

And thanks for the note about other class I dielectrics!

[T3sl4co1l]

Yes, besides the shunt measurement of course!  A thru-measurement may be interesting for noise isolation purposes; though a few nodes inbetween may be desired to introduce extra trace inductance or intentional filtering, which I mean that trace could just be sliced up by hand, but maybe that would be more like a separate PDN testing board -- fair enough.

Tim

[Alex6]

To create an impedance-frequency profile, choose two or three capacitor values. As a result, the peaks brought on by capacitor ESL dominance at high frequencies are reduced. Electrolytic capacitors, many uF or a few 10s uF, should be placed next to power pins during PCB assembly (spam link removed). Use ceramic capacitors close to power supply pins with low power-ground loop inductance for the best noise reduction. I think it's better to consider LICCs for improved performance. To lessen parasitic effects, give priority to small capacitor packages. Tantalum capacitors have a greater ESR but are still suitable. In this application, stay away from mica and metal film capacitors.