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MC34063 high voltage dc-dc boost converter

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magic:
Re-run the simulation and see if the predicted fall time really is in tens of nanoseconds.

My guess is that it's several milliseconds a microsecord ;)
Because it should coincide with the flat part in the middle of gate waveform falling edge.

You really need that turn-off speedup before you can start to worry about FET specs. And even then there is nothing to worry about at such low frequencies. 100ns repeated at a few tens kHz is only a few ms total per each second.

T3sl4co1l:
Datasheet rise/fall times aren't so much intrinsic to the device, they're typical of the drive conditions.  You'll see a lot of Fairchild datasheets with R_G = 25 or 50 ohms, even big transistors for some reason, which of course get laughable times like 400ns.  Typically you use a gate driver IC with an output resistance of a few ohms, and the rise time is in the 10s of ns.

Regarding the sim, the inductance looks awfully large.  Consider how much dI is obtained in the, what, 4us or so expected on-time, at 24V and L.  dI = V dt / L

Tim

dazz:

--- Quote from: magic on January 01, 2020, 05:00:56 pm ---Re-run the simulation and see if the predicted fall time really is in tens of nanoseconds.

My guess is that it's several milliseconds a microsecord ;)
Because it should coincide with the flat part in the middle of gate waveform falling edge.

You really need that turn-off speedup before you can start to worry about FET specs. And even then there is nothing to worry about at such low frequencies. 100ns repeated at a few tens kHz is only a few ms total per each second.

--- End quote ---

Exactly right. 1.15us until it reaches the flat portion of the falling edge. What would be the explanation for this, please? Shouldn't it be closer to the 45ns that the datasheet indicates? I don't know, but looking at the wave form of the gate signal, it doesn't look to me like the time spent in the linear zone is negligible at all, if that's what you meant. What am I missing?

dazz:

--- Quote from: T3sl4co1l on January 01, 2020, 05:18:43 pm ---Datasheet rise/fall times aren't so much intrinsic to the device, they're typical of the drive conditions.  You'll see a lot of Fairchild datasheets with R_G = 25 or 50 ohms, even big transistors for some reason, which of course get laughable times like 400ns.  Typically you use a gate driver IC with an output resistance of a few ohms, and the rise time is in the 10s of ns.

Regarding the sim, the inductance looks awfully large.  Consider how much dI is obtained in the, what, 4us or so expected on-time, at 24V and L.  dI = V dt / L

Tim

--- End quote ---

Oh, right. I totally forgot about the transformer inductances. LOL
The thing is that I've been foolishly trying to get the simulation working properly with the old 400V 10A mosfet. So I started trying stupid things like increasing the inductance of the transformer until I finally realised I needed another mosfet... and then I totally forgot about the transformer  :-DD I'll fix that now.

T3sl4co1l:

--- Quote from: dazz on January 01, 2020, 05:25:33 pm ---Exactly right. 1.15us until it reaches the flat portion of the falling edge. What would be the explanation for this, please? Shouldn't it be closer to the 45ns that the datasheet indicates? I don't know, but looking at the wave form of the gate signal, it doesn't look to me like the time spent in the linear zone is negligible at all, if that's what you meant. What am I missing?

--- End quote ---

What's the test condition in the datasheet?  R_G or R_S or something.

What is the resistance here?

What is the gate capacitance?  (Why is that the wrong question to ask?)

What is the gate charge?  Gate capacitance equivalent?

Tim

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