Author Topic: MC4517 DRAM  (Read 330 times)

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Offline RichardcavellTopic starter

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MC4517 DRAM
« on: March 13, 2023, 01:02:18 pm »
Hi. I’m a retrocomputing enthusiast, and I’m investigating the TRS-80 Color Computer. I’ve found a datasheet here: https://orchidsound.com/mcm4517p12-dram-16-384-bit-16k-x-1-120ns-pdip-16-motorola/

I wonder if I’m reading the datasheet correctly.

1. Is it correct for me to consider that the 7 bit row and 7 bit column addresses could be concatenated into a 14 bit address?
2. Since the chip provides only 1 bit of memory per access, would it be typical to arrange 8 of them in parallel?
3. The datasheet says that it dissipates 14 mW (Standby). What exactly does standby refer to?
4. It has 3-state data output. Does this mean that the default output is high-impedance? When does it produce this output?
5. It has early-write common I/O output capability. What does this mean?
6. The refresh is said to be 64K compatible. I don’t understand what this means.
7. Does it have to be refreshed every 2 milliseconds?
8. It has a hidden /RAS only refresh capability. What does “hidden” mean?

Richard

 

Offline wasedadoc

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Re: MC4517 DRAM
« Reply #1 on: March 13, 2023, 02:20:33 pm »
Why do you need answers to all those questions?  If those DRAM chips were used in the computer the parameters were of concern to and were taken into account by only the original designer of the computer.

Yes they have 14 address bits.  The chip does does have enough pins for all of those so 7 pins double up.  7 address bits are presented to them along with a signal on the Row Address Strobe pin saying "grab these 7 as part of the address".  Then the other 7 bits are presented to the same pins and a signal on the Column Address Strobe says "grab these as the other 7."

Yes 8 chips in parallel to give 8 bits.

Yes 3-state means the output can be high impedance so the 8 chips can be connected to another 8 such chips to have more than 16 Kbytes.  And they can be connected to the outputs of the ROM chip or to outputs the keyboard chip, joystick ports etc.    Only one  device on the bus is enabled at any one time.  Typically done with a Chip Enable or Chip Select pin.

Yes dynamic RAM stores charge on a tiny capacitor for each bit.  The charge leaks away so has to be rewritten frequently.
 

Offline floobydust

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Re: MC4517 DRAM
« Reply #2 on: March 13, 2023, 07:00:49 pm »
Fujitsu MB8118 is an alternate, -12 or -10 speed.
 


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