but does clearing the hardware interrupt flag allow other interrupts of equal or lower priority to fire?
No.... Another interrupt flag may be set in the interim. But not until you exit ISR can another equal/lower ISR flag be acted upon by its own ISR. Hence, while any piece of ISR is being executed, there will be latency in response to a flag being set of equal or lower priority.
You can write the code, right in your own ISR, to poll for a "higher (by your definition)" interrupt flag, and to abandon current ISR.
if not, then does it matter if the interrupt flag is cleared upon entering the ISR or cleared right before exiting the ISR?
It might matter. In case you want this ISR subroutine to immediately repeat if the condition is retriggered while ISR is still executing or not.
The main reason to do it up front, though, IMO, is so you don't have to cover it multiple times, in case of multiple branches in the ISR.
Your needs may be unique. You can certainly write good code that doesn't follow the "short ISR" rule. It depends what you need the micro to do. As long as you understand it, you can achieve your result anyway you want.
If your code may get more complicated later, it might be nice to use timer interrupt set for 10ms, rather than simply set timer for 1 second and check the timer generated flag in main code loop. In ISR, you can increment multiple counters. In this way you can use a single timer for multiple events. When the "LCD timer counter" reaches 100, set your own flag. This can stretch your peripherals and reduce time spent looking at datasheet. Or you could set it so that some order of 2 will equal 1 second. And let the counter freely increment. Everytime bit X change state, set that user flag. Evertime bit Y changes state, you might have something else periodically firing at a different rate, which is some order of 2 different in period, etc. Now you got multiple concurrent timers out of a single post scaler.