Electronics > Beginners
Mixed signal board: split or single ground polygon?
Sparker:
I know that this topic is old as hell :horse:, some recommend to have analog and digital ground, others recommend having a single polygon. I'd like to have some advice regarding my PCB.
So, what I have is: two-layer board, 3xAD7685 ADCs chained with serial interface, an STM32 MCU and an Ethernet PHY. The ADCs are at the top of the board, Ethernet is at the bottom, MCU is in the middle, and power supply is at the bottom left. Initially I thought to split the grounds, as shown on the picture, leaving a single bridge under the tracks of the serial interface. But I've seen it many times at this forum that it's better just to have one polygon.
What should I do? :-//
ejeffrey:
The answer is old as hell too: regardless of ground plane design, the most important thing is to keep your analog signals and digital signals and their return paths separated from each other in your layout. If you do that properly, then considering your circuit in isolation there shouldn't be any current flowing across the boundary so it doesn't matter if there is copper there or not. If you do it wrong, your circuit will perform badly in either case.
There are at least two important caveats to this:
A plane of metal with a slot cut out of it is an antenna. So for EMC purposes, a solid ground plane is preferable.
For low frequency / precision DC the return currents are not so well confined by the path of least inductance. A split plane can help in this case.
Generally I am in the "use a single ground plane" camp unless you are absolutely sure you need to split it.
abraxa:
From the pictures it's a little hard to see what's going on in the upper half but it *seems* as if the serial lines shared between the top and the bottom span quite a stretch across the top part and also the bottom part. This could allow them to pick up energy from the bottom half and transmit them to the upper half. I'd say it's unfortunate that you placed the STM32 in such a way that the used ADC pins are at the bottom, not the top. Now you not only have two ADC interface traces form half a loop, they also run right into the area with lots of digital I/O (think of the ground currents) and even run in parallel to some of the ethernet I/O for a bit.
I'm not an EMC expert myself but if EMC is of concern then it *might* be worth to consider adressing this. Turning the STM32 by 180 degrees would essentially mean to re-do the entire layout, though...
Sparker:
Thanks for your feedback!
abraxa, you are right, the ADC serial interface traces run as you have described. Unfortunately there is not much I can do about it. If I flip the MCU 180 degrees, then the whole high-speed bus for the Ethernet would have to run around somehow, and I must place the Ethernet jack as shown on the picture, that is, facing up (or down) along the vertical axis of the board. EMC certification is not of concern, I just don't want the digital noise ruin my signal which is fed into the ADCs, so I keep Ethernet and ADCs away from each other. Here is a better picture showing the ADC interface lines. Sorry for the bad quality in the other picture.
--- Quote ---For low frequency / precision DC the return currents are not so well confined by the path of least inductance. A split plane can help in this case.
--- End quote ---
What is not very clear for me about the split plane design in my case is , since I have inserted this bridge between the planes, will the DC current of the ADC domain return to the power supply through its own plane on the left at the top side(check picture of the first post), or through the bridge and then through the plane of the MCU domain? I guess it would go partly both ways, so does splitting planes make any sense in my case? :-// I guess not. What do you think?
In my application I care about the band of DC...300 kHz or so, which is almost DC.
abraxa:
--- Quote from: Sparker on November 11, 2018, 04:17:43 pm ---What is not very clear for me about the split plane design in my case is , since I have inserted this bridge between the planes, will the DC current of the ADC domain return to the power supply through its own plane on the left at the top side(check picture of the first post), or through the bridge and then through the plane of the MCU domain? I guess it would go partly both ways, so does splitting planes make any sense in my case? :-// I guess not. What do you think?
In my application I care about the band of DC...300 kHz or so, which is almost DC.
--- End quote ---
The DC return current isn't of relevance here since it doesn't create a changing magnetic/electric field that can influence other traces, so there's no need to worry about where the DC return current flows. The supply current is of much greater importance but from what it seems you already have added bypass caps to each ADC. Adding a ferrite bead to the ADC supply line also doesn't hurt, not sure if you have that already or not.
Where does the 300 kHz figure come from? Is that a clock frequency? Keep in mind that it's not the clock frequency that determines the highest frequency to be concerned about but it's the rising/falling edges - their slew rate determines the frequency components you'll see across the traces.
If you're really very concerned about ADC performance even before measuring it, you could always add footprints for passive filters to the ADC I/O lines. If you find that the performance is not as good as you need it to be, you can then add filter components to these footprints. Those should filter out any "high" frequency components relative to the signal you need to see. It's not something I see often but it is doable if the signal and noise frequencies are far enough apart.
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