Mixing CMOS and TTL gates - for ex 74HC with NE555

[Saimoun]

Hi

Just wondering if there are any issues with mixing TTL and CMOS chips?

I'm designing a project with a 74HC14 (schmitt trigger inverters) and 74HC00 (nand gates), as well as a 555 timer. The gates are the "HC" version and not the "HCT" version (which "accepts TTL levels").

In the circuit I have both gate_out->555_in, and 555_out->gate_in (so you could say both CMOS_out->TTL_in and TTL_out->CMOS_in)

I understand that all gates should be of the same family, it's easier anyways. But what about a 555 timer for example? Should I chose a LMC555 instead of an NE555?


Any thoughts?
Thank you

PS: the design (unfinished) is here: https://www.eevblog.com/forum/beginners/sending-a-digital-signal-with-an-rc-circuit/msg5158056/#msg5158056
(but these questions are more general so I thought it deserved a new topic)

[Ian.M]

A bipolar 555 can be marginal at 5V as its output, if loaded, may not go high enough to reach a valid CMOS logic high level.   A pullup resistor on the output can fix that, same as when connecting a bipolar TTL output to a 5V CMOS input which doesn't have TTL thresholds.  The high shoot-through current of a bipolar 555 can also cause glitches on the output pulse edges, possibly causing double-clocking of CMOS circuits.

[schmitt trigger]

If this is a one-off project for personal use, I would follow Ian’s advice and call it a day if the project works correctly.
However, for a more robust design, replace the 555 with its CMOS version. You won’t break your wallet by doing so.

[Saimoun]

Thank you both for the replies.

I understand   I actually read more about it and found this PDF - https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf - in particular page 4, which shows the levels of CMOS and TTL.

Though I have to say I'm not sure I fully understand why TTL output high cannot go higher than 2.4V? For ex I found this diagram of a TTL inverter (attached below)

If the input is low, the output is high, coming from a 5V supply through a 160ohm res, a saturated NPN and a diode.
Say we connect this to a CMOS input, which is basically a mosfet gate, i.e. very low current needed.

With very low current the voltage drop through the resistor, the NPN and the diode will be very low as well, say in total <.5V, so that would mean an ouput of 4.5V minimum...  Or am I missing something?

[retiredfeline]

It's 2 Si diode drops so actually about 3.7V. 2.4V is the specified minimum for logic 1 at a TTL input. Any difference improves the noise margin.

[Kleinstein]

The 2 diodes would give a drop of some 1.4 V. In the measured output curves of typical TTL chips one gets some 3.5 V out at no load current. However to be away from hum one would need a bit reserve / accepts some (capacitive coupled) load. So the no load case does not really apply.

At least in the schematics I have for the NE555, there is a darlington output with an BE resistor. So at light load the NE555 may give out a bit more (close to 4 V) than a normal TTL chip.

The 74HC14 seems to have a threshold a little lower than normal CMOS logic. So the NE555 is likely still OK. The lower level may still lead to an slightly increased supply current.

[Saimoun]

Awesome to know!! Thank you both for the replies