Electronics > Beginners
modern TTL/Logic-gate/74xx
ebclr:
You may have many hundreds of 74 series chips, on an FPGA, without writing a single VHL line, only drawing the schematics,
hamster_nz:
--- Quote from: ebclr on October 08, 2019, 09:16:20 pm ---You may have many hundreds of 74 series chips, on an FPGA, without writing a single VHL line, only drawing the schematics,
--- End quote ---
Hundreds? Nah, many thousands!
I once worked out that the small FPGA was equivalent to a breadboard the size of a garage, and a (then) large but still obtainable one was equivalent to a basketball-court sized breadboard - complete with 100s of impossibly accurate wire-running gnomes.
The problem with schematic entry is the additional information required. Rather than "C <= A AND B", where A B and C are 8-bit wide buses, you have the following data to manage:
This is an AND gate "AND_1", at (x,y) with rotation of (r), and connections called A, B and C
A run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
his is an AND gate "AND_2", at (x,y) with rotation of (r), and connections called A, B and C
A run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
his is an AND gate "AND_3", at (x,y) with rotation of (r), and connections called A, B and C
A run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
B run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
C run from (x,y) to (x,y), with corners at (x,y), (x,y), (x,y) and (x,y).
....
and so on for eight gates required to AND two 8-bit values.
So rather than a few lines of HDL you end up with maybe 120 to 300 bits of data (all the 'x's and 'y's and 'r' and names and labels) that have to be managed manually - sure most of these are mouse clicks and moves, but it still is a lot of information that has nothing to do with the actual function of the design, only it's presentation to the designer.
If drawing schematics is your thing, than this might scratch your itch and keep you busy on a rainy day, but it is too much like doodling in the margins of a notebook...
But by all means start with schematic entry - you will quickly get frustrated by it you will want the "better way" that a higher level symbolic representation offers.
ebclr:
I for sure do the HDL way, but the OP wana buy and solder chips, this will be better than that
rstofer:
It may be worth the time to block out the design and count the chips and interconnects.
ker2x:
--- Quote from: rstofer on October 09, 2019, 02:47:37 am ---It may be worth the time to block out the design and count the chips and interconnects.
--- End quote ---
This is the first time i try an "hardware first" project on my own.
Before drawing any schematic i needed to know what was available (without doing any dumpster diving to recycle old 74xx chips).
The problem of 74xx availability have been solved (74HC chips from On Semiconductor), they're not the cheapest option but they exist.
I find it funny that some Atmel ATTINY cost less than a quad OR gate.
But the cost isn't a factor anyway, the value of the finished product will never worth the money and i'm okay with it, as long as i don't have to invest tons of money upfront (and there is no need for it).
Even if i bought an absurdly overkill Zynq or Artix-7 fully featured dev board.
But since the whole 74xx problem have been solved everyone is telling me to use an FPGA instead.
I may be stuborn, but not stupid (hopefully?) and you know more about electronic than i do and ever will.
The design will depend on the capabilities of the hardware.
If i did it out of logic gate, the CPU would have been a subset of a 6502 + UART.
On an modern FPGA i could have a full 6502 or Z80 (it have been done countless time) and still end up using only a few % of an entry level fpga (spartan, artix).
It's been only a day so i can't decide what to do yet.
BUT, i have an idea ^-^
(of course i may change my mind again)
The original plan was :
- build the cpu using logic gate
- emulate the rest of the computer, and test the subcomponent of the CPU, using a microcontroller
The new plan may look like this :
- Buy a fully featured fpga dev board (a entry-level one, not one with RF transceiver and 8x 10G ethernet, they are super expensive and useless to me)
- Learn and use this fpga, instead of a microcontroller, for the testing and emulation of the non cpu part of the computer.
- Once done, build the cpu out of logic gate, or build it in-FPGA. Or both.
I have yet to decide if i use an FPGA or a (C)PLD, as i mentioned earlier i misunderstood what a (C)PLD was and therefore know nothing about it.
By the way, i'm pretty sure there will be a massive problem interfacing FPGA and 74xx, right ?
noise, impedence, timing, voltage, younameit ?
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