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| modern TTL/Logic-gate/74xx |
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| james_s:
--- Quote from: ker2x on October 09, 2019, 05:17:01 pm --- --- Quote from: rstofer on October 09, 2019, 04:46:02 pm ---I hope you selected the 100T variant rather than the much smaller (in terms of BlockRAM) 50T device. Bigger is better - always! --- End quote --- Of course ^-^ --- End quote --- I actually prefer smaller FPGAs in most cases. I can fit an entire 8 bit computer in a $12 Cyclone II dev board and compile it in under a minute. I have a DE2-115 with a much larger Cyclone IV and it takes several times longer to compile the same design. Lots of middle ground too, but I actually sold off my biggest FPGA boards some time back when I realized I was never using them, the midsized FPGAs are more than adequate for my biggest projects and anything larger is just slower to compile and more effort to work with. I use the smallest ones the most and the biggest ones the least. |
| rstofer:
I built up a workstation with an I7-7700K, 32GB of fast RAM and a 1TB SSD just because Vivado is such a slug. On this machine, compilations are at least reasonable. Way back, with Win 98 and a much slower processor, building a project could take 20 minutes or more. I realize this isn't anywhere near the record but it exceeds my short attention span. Compiling with 8 threads is helpful! I just started fooling around with Quartus for a CPLD using my laptop and it runs pretty quick for a simple project. About 5 seconds for a project that just sets an output bit to '1'. Of course, the chip is tiny with just 32 macrocells. How long could it possibly take? For no particular reason, I have decided to work through this program: http://www.pyroelectro.com/edu/fpga/ Hint for those who follow: When the author says install Quartus 13.0 SP1, don't get adventuresome and try for a more current version. It won't support the Max 3000A series chip which is the basis for the tutorials. There's a reason I know this! The board, USB Blaster and associated bits and pieces is only about $50, delivered, and the Blaster will work on a range of Altera devices. I'm not much of a fan of JTAG programming but maybe things have improved over the last 10 years or so since I last used a JTAG dongle. https://gadgetory.com/index.php?route=product/product&path=66&product_id=126 The reason I like the larger FPGAs isn't so much for the logic, it's for the BlockRAM. There is never enough BlockRAM... |
| wilfred:
Wow it didn't take long for the thread to move off TTL and onto FPGA. |
| ker2x:
--- Quote from: wilfred on October 11, 2019, 06:23:11 am ---Wow it didn't take long for the thread to move off TTL and onto FPGA. --- End quote --- i know, right ? :-// |
| rstofer:
--- Quote from: ker2x on October 11, 2019, 01:02:31 pm --- --- Quote from: wilfred on October 11, 2019, 06:23:11 am ---Wow it didn't take long for the thread to move off TTL and onto FPGA. --- End quote --- i know, right ? :-// --- End quote --- Sorry about that! The thing is, I like digital systems. I REALLY like digital systems and I can't build them from discrete components because the circuit boards would get massive and plentiful and I'm just not into wire-wrapping like I was when I was younger. But when I was younger, I didn't have access to FPGAs. I remember when I started using the Spartan 3 Starter Board with 1 MILLION logic gates. That is a very modest chip by today's standards but think about what you can do with a MILLION gates! That might be similar to somewhere between 10,000 and 100,000 chips. Did I mention I don't have to wire-wrap them? Can you even imagine wire-wrapping 10,000 chips? A minimum of 14 wire-wraps per chip? Probably closer to an average of 30? 3 million connections? Insane! I can easily envision a CPU that would use up the logic in that Spartan 3. Maybe some kind of pipelined RISC processor with an expansive instruction set. Logic tends to bloom when we add in multilevel caches and multiple cores. My IBM1130 project uses about 30% of the logic and just about all of the BlockRAM. For folks who want to play in the digital domain, FPGAs are the way to do it. A single line of code creates a 32 bit register, not 8 wire-wrapped 4-bit D flops and bus drivers or muxes to steer the outputs. |
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