More VHDL help! Compilation errors!

[McPete]

Hi all,

Sorry to be such a pain, but I'm having some trouble getting my latest VHDL project up and running- It's a strobing display, and I'd like some help picking out the lexical/syntax errors I may have created...

Thanks!

P.

Errors;

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
   Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
   Info: Processing started: Thu Nov 03 13:17:59 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pro2ptm -c pro2ptm
Warning: Parallel compilation is not licensed and has been disabled
Error (10500): VHDL syntax error at pro2ptm.vhd(48) near text "CASE";  expecting "end", or "(", or an identifier ("case" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(52) near text "WHEN";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(54) near text "WHEN";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(56) near text "WHEN";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(58) near text "WHEN";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(60) near text "WHEN";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(62) near text "CASE";  expecting ";", or an identifier ("case" is a reserved keyword), or "architecture"
Error (10523): Ignored construct ascii_out at pro2ptm.vhd(65) due to previous errors
Error (10500): VHDL syntax error at pro2ptm.vhd(74) near text ";";  expecting "end", or "(", or an identifier, or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(80) near text "CASE";  expecting "end", or "(", or an identifier ("case" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(85) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(87) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(89) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(91) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(94) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(96) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(98) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(100) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at pro2ptm.vhd(102) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Info: Found 0 design units, including 0 entities, in source file pro2ptm.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 1 warning

Code;

--************************Header section**********************************
--Name: Peter McKinlay
--Filename: project2.vhd
--Description; This is strobing 5x7 LED display.
--Revision Information;
--Date               Initials            Description
--************************ END Header section*****************************

Library IEEE;
USE IEEE.std_logic_1164.All;

Entity counter IS PORT      -- Mod 5 counter, fed from HW Clock at ~32Khz
(             Clk32k                                                     :IN STD_LOGIC;                           --32Khz Clock input from HW
            count                                                      :OUT STD_LOGIC_VECTOR   (2 DOWNTO 0)   -- MOD5 counter output                                 
);         
END counter;

ARCHITECTURE behav1 OF counter IS
SIGNAL count_op : STD_LOGIC_VECTOR (2 DOWNTO 0);      -- Internal variable
BEGIN
thecounter : PROCESS (Clk32k)
BEGIN= '1'
   THEN count_op <= "000";
      ELSE                           
IF Clk32k'event AND Clk32="1"
   THEN count_op <= count_op + "1"; -- Rising Edge Trigger   

END IF;
END IF;
count <= count_op;
END PROCESS;
END behav1;



ENTITY column IS PORT -- Column strobe control
(               count                                                   :IN STD_LOGIC_VECTOR (2 DOWNTO 0);                                 -- Input from counter
               colout                                                :OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);               --Output to column control HW
END column;

ARCHITECTURE behav2 OF column IS
      
IF count_op(2) <= '1' AND count_op(1) <
BEGIN

CASE count IS
-- Column 1
WHEN "000" =>Colout<= "11110";
-- Column 2
WHEN "001" =>Colout<= "11101";
-- Column 3
WHEN "010" =>Colout<= "11011";
-- Column 4
WHEN "011" =>Colout<= "10111";
-- Column 5
WHEN "100" =>Colout<= "01111";
--ERROR
WHEN OTHERS =>Colout<= "11111";

END CASE;
END behav2;

ENTITY ascii_out IS PORT   --Row Strobe control
(ascii                                          :IN STD_LOGIC_VECTOR (3 DOWNTO 0);   -- input vector from counter and ASCII switches
rowout                                       :OUT STD_LOGIC_VECTOR (6 DOWNTO 0);   --Output vector to row buffer HW
count                                          :STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END ascii_out;
 
 
 ARCHITECTURE behav3 OF ascii_out IS
 BEGIN;
 
 SIGNAL posit                                 :STD_LOGIC_VECTOR (6 DOWNTO 0);
 
 posit <= rowout & ascii;

 CASE posit IS
 --A
 --Row 1
when    "111100000" =>      rowout   <= "1100000";
 --Row 2
 when "110100000" =>      rowout   <= "1011011";
 --Row 3
 when "110110000" =>      rowout   <= "0111011";
 --Row 4
 when "101110000" =>      rowout   <= "1011011";
 --Row 5
 when "011110000" =>      rowout   <= "1100000";
--etc...

END CASE;
END behav3;

[joelby]

This line seems to be missing some bits:

IF count_op(2) <= '1' AND count_op(1) <
BEGIN

The 'if' statement needs a 'then' and 'end if' and the 'begin' needs a 'process'.