Multiple voltage levels required for modern electronics.

[Dave Turner]

Hi all,

OK I admit that I'm still living in the past when TTL logic, never mind RTL & DTL logic, was all the rage. Silicon based logic where VCC was 5V. Low logic level was under 0.8V  and high above 2.4v (if memory serves correctly) and the excess heat from the required power was enough to heat your house. However my point is that I was taught that a silicon P-N junction gave a voltage drop of .65 to .7V. Germanium based technology was 0.2V or thereabouts but much more expensive.

So why are so many different voltages required to power FPGA packages for example?

I'm guessing that it has something to do with the speeds that everything runs at these days with the issues that inductive and capacitive loads/effects have on a circuit particularly with trace lengths. Hence biasing at controlled voltages close to the actual chip itself. I'm further guessing that it is impractical due to die size or heat dissipation to incorporate the necessary circuits on board the chip.

You guys who know - just how far out with my speculations?

regards

Dave

[Benta]

You're on the right track.
The issue with high density FPGAs (or MPUs or memories) is the technology/geometry. At 18 nm or less, it's not viable to use 5 V or even 3.3 V, as this would be prone to flashover in the chip. Hence the low voltage supplies.
On the other hand, I/O at eg, 0.9 V is impractical, so larger transistors are used at the edge of the chip and given higher supply voltage, also to provide some drive current.

Integrating the voltage regulators on the chip is impractical, as linear circuits have completely different geometries and processing steps.

Additionally, FPGA manufacturers always go for "maximum aperture size", a term for the largest chip area you can reach in the stepper cameras (this is only relevant for the newest product families), so even if the silicon technology would allow for linear circuitry, it would limit the size of the logic array.

A third consideration is power consumption, where it is desired to spend as much on the logic as possible. Power losses from voltage regulators are better left outside.

[T3sl4co1l]

First of all, nobody uses TTL, so purge that from your memory.   Fortunately, CMOS has been around just as long, so that should be just as familiar to you, no?

And, just as 74HC is faster than CD4000, 74LVC is faster still, and 74ABT, and so on as you go down in scale.  And as the logic families have gone, contemporary ASICs have even better performance thanks to no requirement to drive pins at every stage.  As you go down in scale, the transistors get smaller, the currents get smaller, and the voltages go down too.  Higher doping is needed for thinner junctions, which limits supply voltage; gate leakage in ever-thinner gates is also an issue (high voltages across a transistor give hot carrier injection -- that's how EPROMs are programmed).

So, it's typical to have low voltages (0.9 to 1.5V) for core logic, which has internal level shifting to a higher IO bank voltage (2.5 to 5V?) which in turn interfaces with the outside world.

Why hasn't board-level logic dropped much below 3.3V?  Probably because there's still just so damn much that's TTL compatible, still out there.  3.3V CMOS is basically 5V TTL.  You can drive MOSFETs (some) and LEDs directly.  And pretty much everything else is TTL-compatible, say if you're adding a PHY or level translator or what have you.  Going lower in voltage invites more noise sensitivity; 3V CMOS has about 1V of noise immunity, which isn't nearly enough for sending over a cable, but it's also not the tiny margin you'd have with 1V logic.

And, that said, there are plenty of lower-voltage logic families available: a few types of ECL, LVDS, CML...  Some are used in cable-level signalling applications, like USB High Speed, or HDMI.  Notice these are all differential in some way or another, a necessity in the presence of real world noise levels.

Tim

[rstofer]

Just think of every semiconductor device as a collection of capacitors.  To change the voltage on a capacitor takes energy - think heat.  More important, it takes time.  If we want to go fast then one way to hurry up the capacitors is to reduce the voltage swing.

[spec]

The other benefit of a lower voltage is lower heat generation. One of the major problems with high density chips, like microprocessors, is getting the heat out. And as clock speeds keep going up so does current consumption.

Incidentally, MOS take no current to speak of at DC, but at high frequency switching it gulps the current.

The 600mV you mentioned is the band gap voltage of a silicon junction. MOS does not have that and can turn on at 0V even, as in JFETs and depletion mode MOSFETs. 

[bd139]

I naively wonder if this is a weak extrapolation of I=C*dV/dT. To keep I down, you need to make C small (reduce process size to decrease physical feature size), increase dT (slow things down) and decrease dV (reduce operating voltage). Increasing dT is the least popular thing as it decreases deliverable performance so the push is for decreased process size and decreased working voltage.

[tggzzz]

I naively wonder if this is a weak extrapolation of I=C*dV/dT. To keep I down, you need to make C small (reduce process size to decrease physical feature size), increase dT (slow things down) and decrease dV (reduce operating voltage). Increasing dT is the least popular thing as it decreases deliverable performance so the push is for decreased process size and decreased working voltage.

That's part of it, but FPGAs have multiple "types" of output cell some of which have deliberately slower transitition times.

The di/dt in transitions causes voltages across inductors, e.g. in i/o and ground lines. Do the arithmetic and you can see those can be a real problem. ISIS models of the packaging help w.r.t. simulations of the effects.

The energy required for a transtion is proportional to CV². That's particularly important in a large IC's core.

Silicon junctions have a maximum field strength, measured in V/m, before they conduct too much current. Smaller geometries imply reduced maximum voltages.

Hence there are different constraints on the core and the i/o cells, and hence different voltages.

[bd139]

Thanks for the explanations. Makes sense.