Ironically that might cut the other way. But it depends on settings of course.
By default, well -- by default default, it's the same pad on all layers, so it clears at about the head diameter (whatever pad OD is set to, hopefully bigger than this!) on all layers. The pad is physically ripped out of the entire board before other copper is affected, give or take any torn traces or fractured components from the incredible stress you'd have to apply to do that!
If you're using a custom padstack with reduced inner pads, that's less, but still fine -- the screw would have to chew up the hole quite significantly to cause shorts (say 20 mil annulus + 10 mil clearance?).
By default, unconnected inner pads are removed (and if you don't do it in the source, your fab will likely recommend such -- or for the low cost protos, they may simply do it automatically without notification!), leaving both the annulus and clearance as empty area -- again a significant clearance around the hole, even if custom.
Unless you've removed the pads entirely (typically, set inner pads to 0 or hole size), in which case it will be simply the inner layer copper-hole clearance, whatever that's set to. Which may be rather small, and this can be a hazard for fab (drilling + registration tolerance) as well as damage.
FYI, I've used this trick (reduced inner pads that are optimized out of the design anyway) in some special circumstances, like tight thermal via patterns while allowing inner planes (not connected to the vias) to pour between them (whereas they would be broken by default via padstacks). Just reduce the inner pads a modest amount, don't set them to zero. No problem.
Tim