Author Topic: NAND gates open collector testing issue  (Read 873 times)

0 Members and 1 Guest are viewing this topic.

Offline gkmaiaTopic starter

  • Frequent Contributor
  • **
  • Posts: 534
  • Country: nz
  • Electronics Hobbyist
NAND gates open collector testing issue
« on: April 27, 2019, 07:36:39 pm »
I am trying to test this NAND gate with an open collector.

http://pdf.datasheetcatalog.com/datasheet_pdf/national-semiconductor/DM5438J_to_DM7438N.pdf

If you look at my images you will see when one of the gate inputs are LOW the output goes LOW.

When both inputs are HIGH I should be getting a LOW input, but that is not happening.

Obviously doing something wrong here. Can anyone give me a light?
 

Online PA0PBZ

  • Super Contributor
  • ***
  • Posts: 5259
  • Country: nl
Re: NAND gates open collector testing issue
« Reply #1 on: April 27, 2019, 07:44:35 pm »
I see nothing wrong here, your LED is connected to +5V so it will light when the output is low.
Keyboard error: Press F1 to continue.
 

Offline gkmaiaTopic starter

  • Frequent Contributor
  • **
  • Posts: 534
  • Country: nz
  • Electronics Hobbyist
NAND gates open collector testing issue
« Reply #2 on: April 27, 2019, 08:53:18 pm »
Thanks for the answer. I appreciate.

Can you please help me understand and confirm a few things?

1 - Because it is an open collector gate my LED anode should be connected to +5v and the cathode to the gate output.
2 - If it was NOT an open collector I would have to connect my led cathode to GND and the anode to the gate output.
3 - On open collector gates when the output is LOW it allows the current to flow from +5v through the LED then out to GND.
4 - On open collector gates when the output is HIGH it works is stops the current from flowing +5v through the LED then out to GND.

Then one question:

Why when the gate inputs are X (disconnected from either Vcc or Vss) my output is LOW?
 

Online rstofer

  • Super Contributor
  • ***
  • Posts: 9963
  • Country: us
Re: NAND gates open collector testing issue
« Reply #3 on: April 27, 2019, 09:25:28 pm »
Because you can't allow inputs to float.  More often than not, they float high.  On CMOS logic circuits they float to the mid-voltage level and the magic smoke pours out of the package.

With TTL, you never want to pull upward.  Even if you have a totem pole output, you would still organize the gate to pull the LED cathode down.

Look at IOH and IOL on page 2:  The low output (sink) current is 16 mA but the high output (source) is only 0.8 mA.

https://www.jameco.com/jameco/products/prodds/49146.pdf
 
The following users thanked this post: gkmaia

Offline Nusa

  • Super Contributor
  • ***
  • Posts: 2418
  • Country: us
Re: NAND gates open collector testing issue
« Reply #4 on: April 27, 2019, 09:28:49 pm »
When an input is left unconnected, it's called "floating". Unless there's an internal pull-up or pull-down or has specific behavior defined in the datasheet, its state is indeterminate. It might be high, it might be low, it might switch unexpectedly. The ambient temperature or humidity might even be a factor.

For your IC, the datasheet defines a LOW input as a max of 0.8V and a high input as a min of 2V. What voltage is an unconnected input?
 
The following users thanked this post: gkmaia


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf