How this is supposed to help when there is no such thing on positive side? Making this on GND side only does not make much sense, especially when load is pulling output to the GND anyway. Not to say output mosfets have quite large RDS(ON) to make much difference.
They could have done both power and ground but I assume they were only concerned with the ground lead inductance as the outputs were pulled low. It is common for only the performance of one edge to matter.
Yes, the 74HCxx series have an on resistance of 38Ohms, which won't make much difference. I can see it making more of a difference with something really high speed, such as an FPGA though.
It is not the ESL [Update: I meant ESR] of the ground (or power) connection which matters; it is the parasitic inductance.
And since the added connections to ground in this case each have the same series resistance as the output driver, they are still useful in lowering the inductance to ground.
Later logic families moved the ground and power connections to the middle of the lead frame and eventually added multiple ground and power connections. But FAST and AC logic were plenty fast enough to have their performance limited and I suspect in critical applications such as this, HC logic was fast enough also or at least Hameg thought so. (1)
(1) This is actually one of the disadvantages of fast CMOS logic families compared to fast bipolar logic. The constant current output characteristics of a bipolar transistor output stage yield a better ratio of rise/fall time to delay time. For equal delay time, the faster RC output characteristic of CMOS is makes it more sensitive to power supply impedance because of higher dI/dT.