Improving voltage swings of buck boost circuit during current spikes

[Annakin4]

Hello All,

I am working on a board which is basically an analog front end connected to a beaglebone, along with a power supply with battery management and a buck boost circuit. Whenever my beaglebone takes a gulp of current which is pretty often, I get a voltage change of 104mV on the output, which lasts 600us, along with much smaller 40mV dips lasting 80us regularly, it seems to line up with an activity LED blinking but hard to tell. Note there is a Pi filter in front of the frontend as well, and it is doing its job. If the beaglebone is off, the rail is as clean as a whistle.

I understand that this is expected behavior as according to the datasheet of my 5V buck boost FAN48610 (https://www.onsemi.com/pdf/datasheet/fan48610-d.pdf), and I understand I should have used a linear regulator for the frontend and used a much lower voltage, however I just need these 30 boards to perform better, and I'm hoping one of you may have a magic solution to improve my data quality. (Starting buck setup- 2 x 22uF on the output, 0.47uH inductor, 11uF on the input)

So far I've just brute forced the issue by adding extra 22uF ceramic caps to the input and output of the buck, and before/after the beaglebone, and put two inductors in parallel in a futile attempt to increase the amount of current which can be stored in the loop while decreasing resistance with the new caps, and I've been searching for caps with a much slower response time but dont have much handy. I have verified the buck is the issue by powering the device from my bench supply to the input of the buck, so the switch in the charger is not giving me grievances. Thoughts?

Thank you,
Sam

EDIT: This image shows the output of a buffering op amp which is a division of the source voltage from a voltage divider, silly me sorry, same waveform on the positive rail, just Vmax 5V instead of 4V

[T3sl4co1l]

What effect is that having on your AFE?  Do you not have adequate PSRR in its components, or design?  (A voltage divider from +V would certainly be a case of ~zero PSRR, and a prime opportunity for improvement.)

Yes, it looks like a noticeably resistive output (Vout changes with Iout) is characteristic of that regulator; other than replacing it with a tighter-regulating part, the next best thing you can do is put an LDO after it.  Preferably one claiming good high-frequency performance (as this area is particularly lacking among most LDOs).

Also how much of that affects the Beaglebone itself, is its analog VREF derived from the same supply or anything?  You may have to hack the boards further, or use an entirely different platform, to get acceptable performance.  Depends.

Tim

[Annakin4]

Thank you for your response Tim, attached is the output of our AFE, I should have included the Y axis but the spikes are the issue more than the average noise if that makes sense. Im not sure about my PSRR tolerances in my parts honestly. The issue is the rail effects the reference voltage, on my 0.75V reference it seems quite clean, while the 4V reference seems to be the issue, which was the capture attached to the original post. These references are fed into differential amplifiers, and a micro acting as a ADC (I know, not great, not my original design, after these boards I'm doing a total overhaul with a proper ADC and a nrf53 to replace the beaglebone.)

[T3sl4co1l]

Okay but what's the time scale, does that actually correlate with the earlier observation?  How many LSBs is that, and how much noise is tolerable for the application?  I have absolutely no idea what to go on here...

Tim