EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: SlowBro on April 24, 2017, 06:02:17 pm
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I'm building a power control circuit for a Raspberry Pi that uses a CD4043 latch, and I think I should be resisting static/noise on the inputs (especially the reset input) to prevent accidental power-offs, but I also need to be able to send it deliberate power-off commands. I can't work out how to create a simple circuit using caps/inductors/chokes/resistors/transistors. Please assist.
The concern came because while the circuit does function it's intermittent. I may just have a bad solder joint but I realized that even if that's the case I should filter out noise.
Requirements:
* Momentary button to turn on the Pi
* Noise cannot accidentally turn on or off the Pi; need at least 100ms of press time to activate the latch set input
* Must be able to power the Pi on either battery or 5V USB wall power, which would not be grounded
I'm testing various configurations in Falstad (http://falstad.com/circuit/circuitjs.html). If I use a choke on the input, applying the switch gives an immediate 5V to the latch. If I put a cap and resistor to ground it still gives an immediate 5V. So I'm lost. Maybe I need some kind of FET/cap/resistor combo? Please assist.
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Before you go any further.
Check that all the inputs to the CD4043 are either set to high or low and will never float. Ensure you've used sufficient supply decoupling. The capacitors should be as close to the supply pins of the CD4043 as possible.
Please post a schematic.
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At the moment I have no caps across the supply pins but even if that's the cause I believe I should be filtering out noise. Don't want spurious dropouts due to noise on the reset line.
Schematic I'll have to draw up tomorrow; Would a KiCad be sufficient or do you need a Falstad simulation?
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Oh and yes, all inputs and outputs are pulled low with 1M resistors.
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And Bingo was his name-oh. (http://falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+35.60246606707791+1+5+50%0AR+32+96+32+64+0+0+40+5+0+0+0.5%0As+32+96+80+96+0+1+true%0Ag+224+112+224+128+0%0Ar+224+80+224+32+0+100%0AR+224+32+224+0+0+0+40+5+0+0+0.5%0Ac+128+96+128+144+0+4.7000000000000004e-8+1.1107662251852493%0Ar+176+96+176+144+0+10000000%0Ag+176+144+176+160+0%0Ar+80+96+128+96+0+10000000%0Af+176+96+224+96+0+1+20%0Ag+128+144+128+160+0%0Aw+176+96+128+96+2%0Ax+235+100+310+103+4+12+CD4043%5Cslatch%0Ao+3+64+0+4099+5+0.05+0+2+3+3%0A) Resistor inline, capacitor to ground, resistor to ground, requires the button to be held for 100ms. The FET and resistor on the right represent the latch.
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And Bingo was his name-oh. (http://falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+35.60246606707791+1+5+50%0AR+32+96+32+64+0+0+40+5+0+0+0.5%0As+32+96+80+96+0+1+true%0Ag+224+112+224+128+0%0Ar+224+80+224+32+0+100%0AR+224+32+224+0+0+0+40+5+0+0+0.5%0Ac+128+96+128+144+0+4.7000000000000004e-8+1.1107662251852493%0Ar+176+96+176+144+0+10000000%0Ag+176+144+176+160+0%0Ar+80+96+128+96+0+10000000%0Af+176+96+224+96+0+1+20%0Ag+128+144+128+160+0%0Aw+176+96+128+96+2%0Ax+235+100+310+103+4+12+CD4043%5Cslatch%0Ao+3+64+0+4099+5+0.05+0+2+3+3%0A) Resistor inline, capacitor to ground, resistor to ground, requires the button to be held for 100ms. The FET and resistor on the right represent the latch.
Bad idea. The input of the CD4043 now only ever reaches 2.5V, which is below the minimum of 3.5V for a guaranteed high. The slowly changing slow could also create problems but I haven't read the datasheet in great detail so can't tell for sure.
https://www.intersil.com/content/dam/Intersil/documents/cd40/cd4043bms-44bms.pdf (https://www.intersil.com/content/dam/Intersil/documents/cd40/cd4043bms-44bms.pdf)
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Good catch. Tweaked based on your input (http://falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+35.60246606707791+1+5+50%0AR+32+96+32+64+0+0+40+5+0+0+0.5%0As+32+96+80+96+0+1+true%0Ag+224+112+224+128+0%0Ar+224+80+224+32+0+100%0AR+224+32+224+0+0+0+40+5+0+0+0.5%0Ac+128+96+128+144+0+1.0000000000000001e-7+3.737449246091742%0Ar+176+96+176+144+0+10000000%0Ag+176+144+176+160+0%0Ar+80+96+128+96+0+1000000%0Af+176+96+224+96+0+3.7+20%0Ag+128+144+128+160+0%0Aw+176+96+128+96+2%0Ax+235+100+310+103+4+12+CD4043%5Cslatch%0Ao+3+64+0+4099+5+0.05+0+2+3+3%0A) so that it takes about 160ms to reach 3.7V. I can tweak the values if I need more or less time.
The slowly changing slow could also create problems but I haven't read the datasheet in great detail so can't tell for sure.
Uhh.. the slowly charging slow? By the way this is the latch I'm using.
http://www.ti.com/lit/ds/symlink/cd4043b.pdf (http://www.ti.com/lit/ds/symlink/cd4043b.pdf)
If there are issues with ramping up the input I can insert a comparator.
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What size cap across the latch supply pins?
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Good catch. Tweaked based on your input (http://falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+35.60246606707791+1+5+50%0AR+32+96+32+64+0+0+40+5+0+0+0.5%0As+32+96+80+96+0+1+true%0Ag+224+112+224+128+0%0Ar+224+80+224+32+0+100%0AR+224+32+224+0+0+0+40+5+0+0+0.5%0Ac+128+96+128+144+0+1.0000000000000001e-7+3.737449246091742%0Ar+176+96+176+144+0+10000000%0Ag+176+144+176+160+0%0Ar+80+96+128+96+0+1000000%0Af+176+96+224+96+0+3.7+20%0Ag+128+144+128+160+0%0Aw+176+96+128+96+2%0Ax+235+100+310+103+4+12+CD4043%5Cslatch%0Ao+3+64+0+4099+5+0.05+0+2+3+3%0A) so that it takes about 160ms to reach 3.7V. I can tweak the values if I need more or less time.
The slowly changing slow could also create problems but I haven't read the datasheet in great detail so can't tell for sure.
Uhh.. the slowly charging slow? By the way this is the latch I'm using.
http://www.ti.com/lit/ds/symlink/cd4043b.pdf (http://www.ti.com/lit/ds/symlink/cd4043b.pdf)
If there are issues with ramping up the input I can insert a comparator.
Looking at the data sheet, no maximum rise/fall time for the inputs is specified. Try it with your circuit and see.
What size cap across the latch supply pins?
It's not critical. A supply decoupling capacitor absorbs transient spikes of excess voltage and supplies the circuit during short troughs. 100nF will do but you'll see circuits with values ranging from 10nF to 10µF, often several values connected in parallel. Generally bigger is better but larger capacitors have poorer high frequency characteristics and can cause stability issues with some low drop-out regulators.
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Some thoughts -
1) In general any input to CMOS logic, unless its a Schmidt trigger input or a sampled
comparator input should not be a slow risetime input as that can cause meta-stable
behavior in the internal logic and/or oscillate due to external parasitic feedback due to
C coupling or power supply transients due to high current because there are paths from
Vdd to Vss thru N and P CMOS devices simultaneously on.
http://preserve.lehigh.edu/cgi/viewcontent.cgi?article=1082&context=etd (http://preserve.lehigh.edu/cgi/viewcontent.cgi?article=1082&context=etd)
2) You are using 1 M ohm R's to set CMOS pin logic levels. Leakage when hot, depending
on part and vendor, can cause offsets and false logic levels. Also noise marging is diminished.
As well a 1 M ohm node is hiz Z very susceptible to parasitic C coupling, use a lower value
calculate dof leakage and allowable logic level limits.
Using a LPF followed by a comparator with hysteresis excellent solution.
Regards, Dana.
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Dana I'm struggling to understand what you're saying (still somewhat of a n00b) but I think the solution you're calling for is this (http://falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+35.60246606707791+1+5+50%0AR+-64+112+-64+80+0+0+40+5+0+0+0.5%0As+-64+112+-16+112+0+1+true%0Ag+224+112+224+128+0%0Ar+224+80+224+32+0+100%0AR+224+32+224+0+0+0+40+5+0+0+0.5%0Ac+32+112+32+160+0+1.5e-7+3.543550025723633%0Ar+80+112+80+160+0+10000000%0Ag+80+160+80+176+0%0Ar+-16+112+32+112+0+1000000%0Af+176+96+224+96+0+3.7+20%0Ag+32+160+32+176+0%0Aw+80+112+32+112+2%0Ax+235+100+310+103+4+12+CD4043%5Cslatch%0Aa+80+96+176+96+0+15+-15+1000000+2.5+3.543550025723633%0Aw+80+80+80+0+0%0Aw+80+0+48+0+0%0Ar+48+0+48+48+0+10000000%0Ar+48+0+48+-48+0+10000000%0Ag+48+48+48+64+0%0AR+48+-48+48+-80+0+0+40+5+0+0+0.5%0Ao+3+64+0+4099+5+0.05+0+2+3+3%0A), am I right? I added the comparator inline and now I get a nice sharp square on signal. Well it's an op-amp; Falstad has a comparator but I can't get it to work. In real life I'll use a purpose-built comparator.
I am using high ohm resistors when possible because battery life is a concern. Don't want pull-downs draining me. Since it's DC currents I should not be terribly concerned with impedance or coupling. (Right?)
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Dana I'm struggling to understand what you're saying (still somewhat of a n00b) but I think the solution you're calling for is this (http://falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+35.60246606707791+1+5+50%0AR+-64+112+-64+80+0+0+40+5+0+0+0.5%0As+-64+112+-16+112+0+1+true%0Ag+224+112+224+128+0%0Ar+224+80+224+32+0+100%0AR+224+32+224+0+0+0+40+5+0+0+0.5%0Ac+32+112+32+160+0+1.5e-7+3.543550025723633%0Ar+80+112+80+160+0+10000000%0Ag+80+160+80+176+0%0Ar+-16+112+32+112+0+1000000%0Af+176+96+224+96+0+3.7+20%0Ag+32+160+32+176+0%0Aw+80+112+32+112+2%0Ax+235+100+310+103+4+12+CD4043%5Cslatch%0Aa+80+96+176+96+0+15+-15+1000000+2.5+3.543550025723633%0Aw+80+80+80+0+0%0Aw+80+0+48+0+0%0Ar+48+0+48+48+0+10000000%0Ar+48+0+48+-48+0+10000000%0Ag+48+48+48+64+0%0AR+48+-48+48+-80+0+0+40+5+0+0+0.5%0Ao+3+64+0+4099+5+0.05+0+2+3+3%0A), am I right? I added the comparator inline and now I get a nice sharp square on signal. Well it's an op-amp; Falstad has a comparator but I can't get it to work. In real life I'll use a purpose-built comparator.
I am using high ohm resistors when possible because battery life is a concern. Don't want pull-downs draining me. Since it's DC currents I should not be terribly concerned with impedance or coupling. (Right?)
Yes, that sort of thing will work.
Perhaps you couldn't get it to work because the comparator has an open collector output and therefore requires a pull-up resistor?
Another alternative is the 74HC14 (single/dual gate packages are available in SMT) but it's inverting so the 10M resistor would have to go to 5V and the switch to 0V.
Anyway, it wouldn't surprise me if the whole design can be simplified. If you post the schematic, I might be able to suggest how.
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Oh I've not tested this new tweak so I can't say if it doesn't work. [Edit: Oops. You were talking about the Falstad comparator.]
What I have on physical board at the moment is just a switchbutton pulsing into the set input on the latch, which may or may not have some kind of soldering issue. I'd share the larger schematic but it has several unrelated items and would be more confusing. Still want to see it? [Edit again: Sorry, that request must have also had to do with the Falstad. OK will post it soon.]
The 74HC14 looks interesting, as if it is a dedicated purpose-built version of what I'd pieced together with an opamp, and looks to be what Dana was talking about.
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You are correct about the Falstad comparator. It requires the output be pulled high to operate. Schematic (http://falstad.com/circuit/circuitjs.html?cct=$+1+0.000005+35.60246606707791+1+5+50%0AR+-64+112+-64+80+0+0+40+5+0+0+0.5%0As+-64+112+-16+112+0+1+true%0Ag+224+112+224+128+0%0Ar+224+80+224+32+0+100%0AR+224+32+224+0+0+0+40+5+0+0+0.5%0Ac+32+112+32+160+0+1.5e-7+2.9779377496757067%0Ar+80+112+80+160+0+10000000%0Ag+80+160+80+176+0%0Ar+-16+112+32+112+0+1000000%0Af+176+96+224+96+0+3.7+20%0Ag+32+160+32+176+0%0Aw+80+112+32+112+2%0Ax+235+100+310+103+4+12+CD4043%5Cslatch%0Aw+80+80+80+0+0%0Aw+80+0+48+0+0%0Ar+48+0+48+48+0+10000000%0Ar+48+0+48+-48+0+10000000%0Ag+48+48+48+64+0%0AR+48+-48+48+-80+0+0+40+5+0+0+0.5%0A401+80+96+176+96+0+0_15_-15_1000000_2.9779377496757067_2.5+0_20_10000000000+0%0Ar+176+32+176+96+0+10000000%0AR+176+32+176+0+0+0+40+5+0+0+0.5%0Ao+3+64+0+4099+5+0.05+0+2+3+3%0A).
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How many latches are you using?
What about just making your own RS flip-flop from Schmitt trigger NAND gates?
The CD4093 & 74HC132 have the Schmitt trigger function built-in. If you build latch with it, then it can respond to slowly changing signals with no need for another IC.
(https://upload.wikimedia.org/wikipedia/commons/thumb/9/92/SR_Flip-flop_Diagram.svg/220px-SR_Flip-flop_Diagram.svg.png)
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I read the thread and don't see why a simple debounced momentary push button won't work.
Requirements:
* Momentary button to turn on the Pi
* Noise cannot accidentally turn on or off the Pi; need at least 100ms of press time to activate the latch set input
* Must be able to power the Pi on either battery or 5V USB wall power, which would not be grounded
Seems like a Schmitt trigger gate and a small amount of other parts should do it.
I must be not understanding the problem.
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Hero999 I'm using the other three latches in the IC for something else so to implement your solution would require two chips anyway. (Two quad NAND packages vs a CD4043 and probably an LP339). It seems like six of one and half a dozen of the other. Your option seems simpler though. I like having options.
rdl not sure how that could work? Wouldn't a Schmitt trigger immediately respond to any very short, high signals? And as the button is released it would then turn back off the Pi. Latch is needed to hold the Pi on. The Pi can later send a GPIO signal to turn itself off. Unless I'm just missing something.
It's also quite possible I'm over-engineering this :popcorn:
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Why can't it all be done with the Pi?
Failing that. How about using another, very simple, MCU?
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Long story as short as I can, Pi uses ~50mA when "off" and my power budget is less than a mA, with less than 100uA being ideal. There is no sleep mode on any of the cheap Linux boards. I'm on disposable battery power.
An MCU -- I started down that path when I said hey I can just use a latch. Should be simpler. I think I'd still want to filter noise from the power button (yes? No?), which is the point of this thread. So comparators or Shmitts and an RC circuit on the inputs. [Edit: or in software... hmm... out of curiosity I'm trying it now.]
I may revisit an MCU but this is almost fully complete. That can be plan B. I'm trying to build a product to bring to market so in somewhat of a hurry as well.