Need for 30-200ns adjustable delay circuit

[Mm]

Hello,

I need to delay square wave signal for 30-300ns. Delay should be adjustable (maybe trimmer?). Signal is 5-20Vpp.

Any very simple circuits available? Is delay IC way to go?
Any help is appreciated, thx.

[Berni]

If the square wave is fairly low frequency then all you need is a RC filter followed by a schmitt trigger input logic buffer chip.

You pick an adjustable R or C in the RC to adjust the time constant of it. This will round over the edge on the square wave so that it takes a bit before it reaches the trigger point on the logic gates input. The buffer gate then just cleans it up back into a nice sharp square wave.

[MathWizard]

I haven't tried anything like that, but maybe even just using chained logic gates, and switches, you could add nanoseconds or 10's of nanoseconds from using multiple gates. How many steps or how much resolution did you need from 20-200ns ? If money is no concern than there's probably chips just for this stuff.

I've never noticed or measured the time delay out of any filter circuit I've made. That's not true but, not for making a nice, delayed good copy of a signal. But there must be analog ways to do it too.

[Mm]

If the square wave is fairly low frequency then all you need is a RC filter followed by a schmitt trigger input logic buffer chip.

You pick an adjustable R or C in the RC to adjust the time constant of it. This will round over the edge on the square wave so that it takes a bit before it reaches the trigger point on the logic gates input. The buffer gate then just cleans it up back into a nice sharp square wave.

I forgot to mention that the signal will be between 100KHz and 1.5MHz.

[Mm]

I haven't tried anything like that, but maybe even just using chained logic gates, and switches, you could add nanoseconds or 10's of nanoseconds from using multiple gates. How many steps or how much resolution did you need from 20-200ns ? If money is no concern than there's probably chips just for this stuff.

I've never noticed or measured the time delay out of any filter circuit I've made. That's not true but, not for making a nice, delayed good copy of a signal. But there must be analog ways to do it too.

I would rather go as simple way as possible because the delay needs to be changed fairly often now during the development so somekinda trimmer would be nice instead of adding gates.

About the the resolution.. i would say that max 5ns steps so that I can time things fairly accurately

[Berni]

Well at 300ns that is the period of a 3.3MHz signal. So this gets pretty close to the 1.5MHz you want to delay.

The problem with the RC method is that it can only delay a signal by 90 degrees max, even that is not practical, more like 45 degrees is the most you could practically get out of it. So to delay a 1.5MHz signal by 300ns means almost 180 degrees of phase shift. It would basically invert the signal at that point.

So to get this much shift out of a RC circuit, it would need to be multiple chained together. At least 4 in series. This makes adjustment trickier since you need to adjust multiple components, but you could find a quad ganged potentiometer for this. The logic buffer chips also usually come in 6 channels per chip (like the classic 74 series hex inverter). When set to low the buffers should still be fast enough to meet the 30ns minimum delay if they are the fast variants of the chip.

[Mm]

Well at 300ns that is the period of a 3.3MHz signal. So this gets pretty close to the 1.5MHz you want to delay.

The problem with the RC method is that it can only delay a signal by 90 degrees max, even that is not practical, more like 45 degrees is the most you could practically get out of it. So to delay a 1.5MHz signal by 300ns means almost 180 degrees of phase shift. It would basically invert the signal at that point.

So to get this much shift out of a RC circuit, it would need to be multiple chained together. At least 4 in series. This makes adjustment trickier since you need to adjust multiple components, but you could find a quad ganged potentiometer for this. The logic buffer chips also usually come in 6 channels per chip (like the classic 74 series hex inverter). When set to low the buffers should still be fast enough to meet the 30ns minimum delay if they are the fast variants of the chip.

Thx for your reply.. I appreciate you taking your time for this.
Current tests implies that most likely the need for delay is going to be about 45ns.
If the delay range is only 30-60ns, would it be easier to make?

[Berni]

Yep 60ns delay at 1.5MHz would make for a 32° phase shift, so it is within the reach of a single stage RC filter.

[Kleinstein]

A short delay can be done with RC. If needed one could have a jumper to add a fixed additional delay stage with extra gates and fixed RC. So one 10-50 ns with a trimmer and optional additional ~ 40 ns fixed for a larger range.

The RC delay may be effected from H/L ratio if the frequency is relatively high.

[iMo]

For delaying of a squared pulses by XXns you would need an adjustable "delay line".
There are even chips for such an applications afaik, just search for them.
Like the older DS1020-100 or DS1020-200..
https://www.analog.com/en/technical-articles/ds1020ds1021-8bit-programmable-delay-lines.html

[jonpaul]

1970s solution with SSI 74C series logic: 1..2 ICs.

 buffer>>RC>>schmidt trigger

  74HC04 abd 74HCU04 as buffers and 74HC14 schmidt.

Jon

[Alex Nikitin]

This might work.

Cheers

Alex

[Mm]

Thank you everyone for helping out. I think the "delay line" seems very nice approach..