generate low noise square wave

[Jinhao]

Hi,

I wonder what is the recommended way to generate a very low drift square wave. Is it viable to generate square wave output by switching between a voltage reference and ground with a mosfet IC? (The voltage reference IC LTC6655 has ultra low drift 20ppm/sqrt(kHr) and I have it for my ADC)

I'm working on a MEMS accelerometer project and need a low drift square wave as excitation (carrier) signal. I currently use Teensy 4.1 FlexPWM to generate the 100kHz square wave. However, I found large drift (<1Hz noise) in the demodulated signal (pic attached, around 100Hz noise is ambient vibration). I suspect the noise comes from the LDO of Teensy 4.1 (TLV757P)https://www.ti.com/product/TLV757P (noise density figure attached below).

More about the project : the schematic in LTspice is attached. Square wave as excitation signal goes through a differential driver (LTC6362) into the differential pair of movable electrodes of MEMS accelerometer (C1 & C2). C3 models parasitic capacitance. The unbalanced charge then feeds into a charge amplifier built around LTC6240. The output is prepared by an ADC driver with gain of 5 and anti-aliasing filter. The ADC (LTC2500, not shown in the schematic) samples the modulated data which is demodulated digitally on my PC.

In my opinion, the entire circuit operates at carrier frequency. The LDO of microcontroller seems to be only place where 1/f noise can be modulated and carried forward. Initially, I suspect the drift comes from charge amplifier, so I replaced it with a zero-drift Op Amp (AD8628). The drift issue still existed and even worse, there was a lot of intermodulation distortion noise.

Any advice or resources is very helpful 

[Ian.M]

Try a 74LVC1G74 single gate D type flipflop wired to toggle, powered from your reference voltage and clocked with double your desired square wave frequency. If the incoming clock frequency is stable, its Q output should give a very accurate amplitude near-exact 50% duty cycle square wave.

[Jinhao]

Thanks for your suggestion .

I started my searching from analog switches and eventually found out I just need to duplicate the CMOS pair of GPIO with my own voltage reference as supply. Voltage translating gates seem to be the available IC closest to a CMOS pair.

I wonder if a simple voltage translating gates as CMOS pair would do the same job. Regarding the clock frequency, Teensy 4.1 operates at 600MHz, so the timing of 100kHz square wave signal should be very accurate. Is the near-exact 50% duty cycle the reason you recommended the D type flipflop?

I have never used logic gates before, not sure what to watch out for. I don't know whether those commercial logic gate ICs come with some fancy features such as ESD or overvoltage protection that would defeat the purpose of low noise.

[Ian.M]

Yes, the flipflop (rather than a simple gate or level shifter) is solely to eliminate any duty cycle bias e.g. if the load on the I/O pin causes slight modulation of the MCU's oscillator frequency.   74LVC gate inputs are generally 5V tolerant (at 3.3V Vcc) so the clock signal from the MCU can overdrive the flipflop's clock input without drawing significant current.  You may need a series resistor matched to the trace impedance to damp reflections that could otherwise transiently double the amplitude of edges and cause the gate input ESD protection structures to momentarily conduct, possibly resulting in excessive noise on gate Vcc (the reference).  Local Vcc decoupling is essential to prevent the reference glitching on rising Q edges due to the current spike required to  charge the output trace capacitance.

[Kleinstein]

A simple gate like 74LVC1G04 or similar should be OK for the level shifting and get less load to the reference. An alternative would be a 74LV4053 CMOS switch - this way the gate drive is even more decoupled from the reference. I don't think one would really need the extra driver for the MEMs unit. At least the LV4053 should be OK to also switch between 2 suitable levels directly.

Ideally one would use the same reference for the ADC and drive side this way the system would be ratiometric and the reference noise would not matter much. It can still be good to have a buffer between the ref and the CMOS gate / switches.

There is always the possibility that there is actually some background acceleration  / vibrations in the building. So it can be hard to tell appart the electrical noise and mechanical background. It may take 2 sensors or a comparison with 2 levels of mechnical isolation.

[n4u]

You should try woth ocxo.

[Jinhao]

Thanks for your reply. I plan to try 74LVC1G04 first for simplicity.

The voltage reference ICs (LTC6655 or LT6657) I plan to use come with buffered output. Thanks for mentioning that.

You are right, I cannot tell for sure if the low freq noise is the actual background vibration. I will buy a non-MEMS very low drift accelerometer to characterize the background noise. But I do feel the noise density of the current LDO is too bad to leave alone. I view the square wave as constant LDO output modulated at carrier frequency. So, when demodulated, the LDO noise would appear in my baseband result.

[Jinhao]

Thank you for your suggestion. I'm actually less concerned about the timing accuracy but rather the low frequency (<1Hz) noise in the amplitude of 100kHz square wave. I might try ocxo at the end of the project. For now, I still want to have some flexibility of changing carrier frequency easily.

[Jinhao]

A series resistor to reduce reflection wave is a good point. I saw a 22ohm resistor is commonly used for this purpose. I don't have equipment to measure trace impedance. I plan to simply add a 22Ohm resistor and hope for the best. :'(

[radiolistener]

low frequency drift and duty cycle are completely different things.

The goal of very stable low drift oven controlled oscillator is a stable frequency for a long period of time, if it have duty cycle variations, but still has stable average frequency over long time period - it's ok.

On the other hand precise 50% duty cycle signal source can have pretty high frequency drift, because it doesn't affect duty cycle.

So, what is the goal - stable duty cycle or stable frequency?

There is also another issue, precise duty cycle requires extreme fast slopes with a very small phase and amplitude noise, because any kind of noise leads to a small duty cycle variations from cycle to cycle.

Also I can suggest you to avoid using MEMS oscillators if you want low drift frequency or low phase noise. These MEMS oscillators have very high frequency drift, it is so bad that you can use it as a sensitive proximity sensor just by measure it's frequency with help of TCXO source for comparison. Just tested one MEMS oscillator from Microchip, and found that I can detect my hand position placed near the pcb with MEMS oscillator

[radiolistener]

I might try ocxo at the end of the project. For now, I still want to have some flexibility of changing carrier frequency easily.

if phase and amplitude noise is critical for your needs, but frequency drift is allowed, you can use simple ultra low phase noise VCXO, they have pretty clean output, much better than TCXO, and don't eat electricity like crazy as it happens with OCXO. 

Also, you're needs to take serious care about power supply filtering for VCXO with using filters, ferrite beads and low noise linear regulator, power supply needs to be placed near oscillator to avoid long wires. Note that such low noise oscillator needs a dedicated low noise power supply.

[Kleinstein]

For the accuracy to looks at it does not look like one has to care that much about the duty cycle and frequency stability. A normal crystal oscillator should be good enough. Chances are the µC is using an internal PLL anyway. A more stable clock would mainly make sense if the PWM signal is externally syncronized to that clock.

The LTC6655 reference has a buffererd output, but this buffer would not help very much against the rather fast switching spikes from the CMOS gate / switch. Similar the ADC ref. input tends to produce some higher frequency injection. So ideally there would be 2 separate buffers or at least LCR filters for both the ADC and sensor driver.

There is another small effect with the capacitove MEMs sensor: The intended drive signal is modulated to detect a capacitance change. The dirve signal also causes a small unwanted electrostatic fore on the sensor. Here also the non modulated part and common mode component can matter. So low frequency noise in the drive signal could actually move the sensor and make it read an acceleration.
So while the read part can be ratiometric and would not care about reference noise one may indeed want a low noise reference. In addition there would be low frequency noise of the LTC6362 driver, that has quite some low frequency noise. I would prefer to directly drive the sensor from 2/3 of an 74LV4053 or 74HC4053 (if a negative drive is needed). In the simulation the MEMs drive signal is shown as 2 pF range, so not really a large load. 

[Jinhao]

Thank you for your informative reply. I guess the "low drift" term I used in the title does not well describe my need. I am okay with my current frequency precision and duty cycle. I am more concerned about the low frequency noise in the amplitude of the square wave for the long term. The critical part of circuit operates in analog domain, so amplitude stability of square wave in my case is more important.

In my opinion, the square wave from a microcontroller is the supply voltage modulated at the square wave frequencies. Based on the microcontroller's LDO datasheet, the LDO output has very high low frequency noise. The low frequency LDO noise amplitude modulated (AM) in square wave appears in the band of interest (700Hz span around 100kHz square wave fundamental frequency). As a results, I saw noise in the baseband of demodulated signal. At least, I think this is cause of the noise in my results. I can be wrong.

In fact, a sine wave as carrier signal would work even better, but square wave is adequate and simpler to generate with my current microcontroller. So basically, I want to generate my low noise square wave with supply voltage replaced by a precise voltage reference to reduce the low frequency noise in amplitude.

[Kleinstein]

The ouput from the µC would have the noise of the LDO and in addition some modulation with the supply current to the µC. So things like an UART of display output could effect the PWM amplitde.
For this reason it makes some sense to have the external switches / driver.

Getting a stable sine wave is more difficult than gettting a stable square wave. So the square wave is probably OK.

[Jinhao]

Yes, the frequency accuracy is okay for me. I'm more concerned about the low frequency LDO noise modulated in the square wave.

LTC2500 gives the example setup in the datasheet (figure attached) without an external buffer. I see LT3040 is the recommended. However, I'm not not sure which parameter to look at for switching load performance. Right now, I see the closed-loop gain for low load varies around 1kHz. Does it suggests it's not suitable for my low current application?

Yes, you are right. I try to minimize the motion caused by drive signal by choosing drive signal at 100kHz much higher than my MEMS 700Hz resonant frequency. keeping the 100kHz motion small is mainly to keep system (especially cantilever beams) in linear region. The 100kHz motion theoretically should not appear in the baseband of interest after demodulation.

Regarding the noise of Op Amp, the noise source of voltage, current and resistance noise are already considered. I studied the offset voltage (Vos) noise yesterday. Vos in LTC6362 will affect the amplitude of my square wave, as you mentioned, a matter of gain error. But the drift and aging of Vos make the gain time varying, hence modulated noise becoming the problem. LTC6362 has 0.9uV/C differential Vos and 45uV/C common mode Vos. The common mode offset can also create a big problem: the mass is virtually grounded, non-zero differential square wave create unbalanced voltage potentials. I am thinking to AC couple the output of charge amplifier (LTC6240) to eliminate Vos effect, AC amplitude is the signal of interest, after all.

Although I want to avoid using LTC6362, as you suggest drive directly with CMOS, I need 1) a reliable way to virtually ground the proof mass to minimize trace parasitic capacitance, 2) have a very clean negative power supply. right now I have a charge pump voltage inverter followed by a regulator. I think the result would be worse without the help of Op Amp's power supply rejection ratio (PSRR). LTC6362 still seems a good choice for now.

[Kleinstein]

The charge spikes from the switches and ADC are rather fast, with the relevant frequencies more in the 1-100 MHz range. The main countermeasure is a capacitor - the regulator would be on the slow side anyway.

A symmetric square wave drive would ideally not cause mechical driving force to the MEMS as the electrostatic force is proportional to the voltage square. So using square wave drive also has a positive side. Depending on the internals there could still be some effect, e.g. with internal DC offsets, phase shifts from not so conductive electrodes and nonliniear MOS capacitance.
The MEMS element would not have just 1 resonance frequency - mechanical systems larger than simple molecules always also have high resonant modes. At the higher frequencies the gas damping is lower and the Q can be quite high. A positive thing is that the higher modes usually don't couple much to a simple capacitive drive. 

To get a symmetric drive from CMOS switches one would either need a symmetric reference (e.g. invert the reference with an extra OP-amp) or have the ground of the MEMS lifted to half the reference voltage. AC coupling the drive signal could also work. One may still need resistors for a defined DC level.
The ADC should be OK with some DC background - if inside the comon mode range.
Having V+ (2.5. V) for the supply of the drive side and for the shift of the common mode signal at the detector side is a problem, as there may be some coupling via V+.  The CM shift should be more like half the ADCs reference.
Also the supply to the 6240 OPamp should be well decoupled from the drive side (filters at both the drive side and the amplifier). At some 100-600 kHz the PSRR is not longer that great and there is parasitic coupling.

The LTC6362 should not effect the amplitude of the drive signal very much. The gain is set by the resistors there. The LTC6362 would more effect the symmetry and may add some low frequency noise to the drive signals.

Switched capacitor circuits to produce a negative supply tend to produce quite some current spikes and this way possible interference. They require good filtering on the output and input side.

[Jinhao]

I really appreciate your expertise. It took me time to study first and then come back to realize my study conclusions are in your comment.

You are right, I mis-understood the PSRR. From the datasheet, PSRR defines the ratio of supply voltage change to differential (input referred) offset voltage, not the gain change. As you said, closed-loop gain is only determined by those feedback resistors. So, for the receiving side, the power noise at low frequency (1/f noise) doesn't seem to be problem because additive offset voltage noise does not affect my AC signal at carrier frequencies. I only need to pay attention to the power supply noise density near my carrier frequency.

The driving side would suffer a lot from the asymmetry (common mode offset from proof mass potential) of differential square wave and suffer a little from the differential offset. half-bridge charge amplifier relies on symmetry after all. It would be great if there is a way to connect the proof mass to the Vocm of differential driver Op Amp without affecting the charge flow of the following charge amplifier, this way, the differential square wave is more symmetric. As you mentioned, the slow varying differential offset drives MEMS at non-middle position which emulates the vibration in MEMS bandwidth and so becomes noise.

I still hesitate to lift proof mass voltage potential. I can't tell why, just feel uncomfortable I guess. 

Regarding the 2.5V supply issue, I didn't mention that 2.5V supply to Op Amp is from a LDO and the 2.5V Vocm is generated from half of 5V voltage reference. My LTspice schematics voltage sources are ideal, so I combined them. On PCB, they are already decoupled.

Regarding the filtering of switched cap, I only have a 10uF capacitor at input. It is powered directly by a Lithium ion battery, same as the rest LDOs. Does this meet the standard of "good filtering on the input side" as you mentioned (I lack knowledge again here regarding filtering)? On the output side, I have a negative linear regulator to filter the noise.

Thanks again.

[Kleinstein]

Only a 10 µF capacitor alone is not yet a filter. It would needan additional series impedance (e.g. resistor or ferrite bead) to get good filtering.
Just a decoupling capacitor, but a low impedance link to the supply creates a combination mulitple low ESR capacitors linked with relatively long traces and thus the possibilty for resonances. The ripple current would also flow over quite some distance to other capacitors and thus also the ground return current. So multiple direct parallel capacitors can also effect the ground.
I know this is my persomal preference, but I like some series elemet (resistor) with all parts that can produce interference or are sensitive. So I like the way many RF circuits are build with local RC filtering with essentially all uses of the supply.

[radiolistener]

If you're using microcontroller to produce square wave, thats a bad choice. The output of microcontroller is very-very noisy. It has overshots and top/bottom part of square wave more looks like sine with random pulses.The source of that noise is not LDO, but microcontroller. The source is inside of microcontroller. For digital circuit this noise is not important, because it appears above or bellow digital threshold voltage. But if you need square wave which is free of amplitude noises, microcontroller cannot produce it.

You can add some digital buffer with a good filtered power supply, it should clean signal from unwanted amplitude noise. But note, anyway the signal produced with microcontroller also have bad phase noise and you cannot remove it with digital buffer. This phase noise is due to architecture of microcontroller.

Microcontroller is the most noisy signal source. FPGA can produce more clean signal, but still lack of signal purity due to jitter limitations. So, if you want clean signal, it's better to use dedicated circuit for that.

[Jinhao]

Thank for your comment. I took some measurement today and indeed saw about 20mV voltage ripple on my VCC line (i.e. battery). I do need some filtering on the input side to localize the charge pump noise.

I found a useful guide on charge pump filtering. So, I plan to use a LC filter as it recommends.https://www.analog.com/en/technical-articles/simple-methods-reduce-input-ripple-for-all-charge-pumps.html

[Jinhao]

Thank you for your comment. You are right, in the next PCB design, I use the micro-controller generated square wave to drive an CMOS gate powered by a precise, buffered voltage reference.

I took some measurement today. The jitter seems okay to me. It reads 360ps for 10us period square wave signal, i.e. max error 18 ppm. Not sure how phase noise would translate to fft noise level, but personally it seems good.

[David Hess]

Using CMOS gates or switches with a reference supply is a good way, but has the disadvantage of poor termination because of the variable resistance of the CMOS transistors.  Driving a capacitive load also tends to upset the reference, although this can be corrected by buffering the reference.

The alternative used in precision pulse sources is to use a parallel termination with switched current sources, which are usually bipolar transistors but could be FETs or diodes for greater DC accuracy.  Switching a current source means drawing current away from it at the emitter or source with the base or gate held at a fixed voltage, so the transistors are used in the common base or common gate configuration which has all kinds of advantages like speed and isolation.