Common mode voltage?

[MaxSimmonds]

Hey guys,

I'm currently working with an ADC (the AD7982). It requires a fully differential input. For this, a previous engineer used the ADA4941. I'm currently trying to understand how it works, by modelling in LTSpice. The application note for the ADA4941 mentions that:



Referring to the circuit diagram:



My confusion is that I don't understand how there can be two common mode voltages, I thought the point of common mode meant it was common to both. So, obviously there's something I'm not understanding.

The application note https://www.analog.com/media/en/technical-documentation/application-notes/AN-1494.pdf gives two equations (the text preceding them is highlighted above). I've simulated the op-amps, and I can't get the values:

OUT_N,cm = 5*0.5 * 2 = 5V
OUT_P,cm = 5*0.5 = 2.5V

So, this says that the common mode voltage on the negative pin is 5V, and the the positive is 2.5V. With a 0V input voltage, OUT_N is 2.5, so I assume this is the common mode voltage their talking about, but it's on the wrong pin (negative, not the positive). But no matter what I probe, I can't see 5V referring to any of the output pins.

Can anyone explain to me the common mode voltage definition for this application? I'm only use to the definition (V1+V2)/2 as being the common voltage, but I don't think that works here.

Thanks guys, attached is the simulation if anyone wants to have a look.

Max

[tszaboo]

You have input common mode voltage x2, and output common mode voltage. You usually dont have that, because an opamp has 2 inputs and 1 output, but this is a special ADC driving opamp.
You will not see 5V on the output, you will see 2.5V+x and 2.5V-x.

[MaxSimmonds]

Hey NANDBlog,

Thanks for replying - I would have thought the same, but if I apply 0 VDC to the input, I would expect +2.5V on the OUT_P line, and -2.5V on the OUT_N line, but this isn't what I'm seeing:



The difference between the two outputs is 2.5V, but they're symmetrical about 0V by 1.25V. Really, what I'm after is how I would set the REF and IN voltages such that I can have a +/-5V input, and an output where the voltage on any such pin doesn't go below 0 or above 5v.

[MaxSimmonds]

I've just noticed an issue in the simulation file (OUT_N should be connected directly to the output of the bottom op amp, not after the 1K resistor. So I'll have a look now, I'm sure that'll change a lot!

[tszaboo]

Hey NANDBlog,

Thanks for replying - I would have thought the same, but if I apply 0 VDC to the input, I would expect +2.5V on the OUT_P line, and -2.5V on the OUT_N line, but this isn't what I'm seeing:

Nono. The ADC common mode input is 2.5V. The OUT_P goes from 0 to 5V the bigger voltage you have on the input. The OUT_N goes from 5V to 0. If you apply 0V on the input, both voltages are 2.5V.

[MaxSimmonds]

Hey NANDBlog,

Thanks for the message. I thought I'd write up quickly the equations I got for the circuit, in case anyone else in the future needs them.



Where G is the gain, set by R2/R2 (as per the original image).

I hope this helps someone in the future!