You need to understand transistors and how they are turned on and off.
The bottom transistor needs a base voltage equal to the output voltage plus 0.6V to account for V
BEIf you want an output of 5V, you need a base voltage of 5.6V. You also need to account for V
CEsat which is about 0.2V so the collector needs to get to at least 5.2V which is also the emitter voltage for the top transistor.
It's the upper transistor where things really turn south. For the emitter to to get to 5.2V, two things have to happen. First, the supply voltage needs to be 5.2 + V
CEsat or around 5.4V. The problem is, the base voltage needs to get to the emitter voltage (5.2V) plus 0.6V V
BE or 5.8V.
If you really only have 5V then you won't see more than 4.2V output on the gate. And this is going to limit the output voltage of downstream gates. The next gate can't get above 3.6V, the one after can't get about 3.0V and so on. When gates were made this way, there were buffers gates inserted to restore the voltage level which slowed down the logic.
You're right, this is a lousy circuit for an AND gate.
When you think about it, you will see that NAND and NOR gates are easier to make and that's why the first numbered TTL device, the 7400, is a quad NAND gate. The 7402 is a quad NOR gate. They do make AND and OR gates (7408 and 7432) but they are much farther down the list and less important.
The NAND gate may still use two transistors stacked but the load resistor is at the top. Worst case, the output will only pull down to 0.4V (two times V
CEsat) but that is low enough to prevent a following stage from triggering so that output is fully high.
Very little logic design actually uses AND and OR. We tend to write the equations as a sum of products (NAND) or product of sums (NOR).
For the 7400, the highest logic LOW input voltage (V
IL) is 0.8V and the worst case output LOW voltage (V
OL) is 0.4V. So there is about 0.4V of margin - the worst case output is 0.4V lower than the worst case input. The lowest logic HIGH output voltage (V
OH) is 2.4V and the worst case logic HIGH input voltage (V
IH) is 2.0V so again, there is about 0.4V of margin. See page 2
http://web.mit.edu/6.131/www/document/7400.pdf