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Need help with Op amp buffer

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Kleinstein:
The DDS chips can give you 0-5 V amplitude directly from the chip. The output is differential with 2 current outputs that usually work with some 50-200 Ohms load to the filter circuit. Some cheap boards may only use one output. So the output amplitude is more like 0.5 V_pp.

So one will usually need more than just a buffer, but some amplification. In addition the output will usually loose half the amplitude to the 50 Ohms termination. So if one wants 5 V out at 50 Ohms the amplifier usually needs to go to 10 V with a 100 Ohms load. This may need a little more current than the normal OPs can easily drive.

To get 1 V_pp at 1 MHz it needs a slow rate of 3.14 V/µs as the derivative of sin(2*pi*f*t) gives the extra factor 2 Pi.

Many modules don't work well all the way to 40 MHz (e.g. limited by the filter, layout). So one may not need to have to amplifier all the way to 40 MHz.

Adjusting the amplitude with the DAC reference usually only works well for a small range.

The choice of the OPs depends one the supply (not all of the fast OPs like +-15 V) and the speed one is comfortable with in the layout.
One could consider something like AD811, AD8051 or some Ti THS... series chips.

hummusdude:
Avogadro...I double checked my circuit and the diodes appear to be in correctly. The offset pins are floating. My understanding is that the offset is useful for fine-tuning +- 15 mV and not required if the accuracy is close enough. I did try a 10k pot on the offset pins with the wiper going to V- and did not see any change.

hummusdude:
Kleinstein...thanks for the analysis. I should have been more specific about my needs. The 9850 board I'm using does give 0-5 v square wave out and 0-1 v sine wave out. I didn't mean to imply that I was going to amplify the sine wave to 5 v. It would be more useful to have the range, i know. But I'm trying to resist scope creep and keep this project constrained to the output of the 9850. Just looking to buffer the signal because the DDS keeps shutting down every time I change the lead connection and the output is so noisy my scope has a hard time triggering. I assume the EDS issue of the 9850 is CMOS related and the jitter might be a lack of shielding . That, and classmates have mentioned that they were able to reduce the jitter by buffering the output.

As for the slew rate issue, it sounds like I can do better than the LM 741 but 40MHz may be a bit ambitious for the scope of the project. I'm okay with that...it's my first project and it's already pretty good. If I can get it stabilized and working consistently it will help with job interviews. I'm attaching a couple of pics for fun. The LCD is driven by an Arduino Uno that recieves serial data from the Mega.

Kleinstein:
The rectangular output has even faster slopes. So the easy way would be to use separate buffers for the sine and rectangular signal. For the digital part something like 74HC04 / 74HCT14 or similar, using 4 gates in parallel could be a simple solution. 4x180 Ohm can combine the outputs and give it an approximately 50 Ohms termination and some protection.

For the sine wave there are plenty of OPs fast than the 741. It can get tricky on the prototype area to go all the way to 40 MHz as the fast OPs also need good decoupling and are often available in SMD only.  An important parameter is the supply that is available. If there is a +-5 V to +-15 V supply I would consider the good old NE5534 / 5532. It should be good to some 5 MHz. One should still have termination (e.g. 50 Ohms)  at the output, even if it is only to isolate the OP from the capacitance of the cable. With a 12 V supply one could use AC coupling to bring the sine signal to about the center and also have the output AC coupled. The supply splitter could be an option too to make it a +-6 V.

For the "noise" / interference, part of this could be due to the cabling. Chances are an electrolytic cap (some 100 µF) near the DDS board at the supply could help somewhat.

The offset pins at the OP are usually there to trim the OPs own offset, usually < +-5 mV. Using them to add more offset can cause problems.

Kirill V.:
Yes, using logical gates as buffers of a logical signal is very reasonable. But does a purely analog buffer not have any advantages here?

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