I think the upper limit is 400k bps for I2C so any LA that will sample at 4+ MHz should be adequate.
I'm not sure what the fastest SPI link runs at but 60 MHz wouldn't surprise me. Any LA that can sample at 1 GHz would be adequate.
In other words, don't run SPI at full speed and plan to probe it with a $10 LA. The thing is, not many people even try to run it that fast so it's up to the user how much they want to spend of going fast.
The inexpensive LAs are a place to start. Get one and learn to work with it. I built the Sump.org LA from a Digilent Spartan 3 Starter Board and it samples at 200 MHz - pretty decent but I was running the FPGA project board at 50 MHz. Not ideal but it worked ok.
https://www.sump.org/projects/analyzer/In terms of FPGAs, the Xilinx Vivado tool includes the capability of defining an Internal Logic Analyzer that runs in the same hardware at the same synchronous clock. This is on the hardware, not simply a simulation. Debugging FPGAs take a lot more creativity to find logic design errors.
For a CPU, implement single-stepping either by instruction cycle (fetch through execute) or by state clock, preferably both. Also implement an address breakpoint that stops the state machine when there is an attempt to access a particular location in RAM. This will let you debug at the source code level, instruction by instruction after you hit the breakpoint.
Before Vivado, I threaded a 32 bit debug bus through all of the components. It was commented out in all but the component under test. I needed a way to get signals generated 3 or 4 layers deep out to the pins.