Actually, LTspice A device digital primitives need a couple more settings to reliably behave as you would expect an ordinary CMOS logic gate to. Ignoring output impedance (as the series 3K3 resistor swamps it), and slew rate (as its negligible with respect to the RC time constant with the MOSFET gate capacitance), you *should* set:
Vhigh=5, Td=14n, Tripdt=2n
in the component attribute editor, which is based on the typical propagation delay of a 74HC74 @5V Vcc.
If you don't set an appropriate propagation delay more complex sequential logic will often fail to behave as expected.
Tripdt controls how closely spaced simulation timesteps are round gate transitions (if nothing else is forcing close timesteps), and is required to get LTspice to honor specified propagation delays and rise/falltimes. See
LTspice Help: LTspice(R): Circuit Elements: A. Special Functions for details of other A device parameters.
N.B. setting separate
Rhigh and
Rlow rather than a single
Rout can make the simulation an order of magnitude slower!
N.B.2. You can use any of the four attributes
Value through
SpiceLine2 for A device parameters, and also control whether or not each attribute is visible on the schematic. In logic designs with a variety of propagation delays, I like to make that visible, though you may wish to put the other parameters that are common to all or most gates in a different attribute and hide them to avoid an excessively cluttered schematic.