EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: 3roomlab on October 31, 2015, 12:51:20 pm
-
while spending some time getting used to a used K2015 THD bench DMM, i got the chance to compare some readings with this post
https://www.eevblog.com/forum/testgear/dmm-adc-noise-comparison-testing-project/msg763062/#msg763062 (https://www.eevblog.com/forum/testgear/dmm-adc-noise-comparison-testing-project/msg763062/#msg763062)
(thanks to Alex and TiN). i then discovered an odd noise problem with my used K2015
under 0.1v range, 10NPLC and 1 NPLC seems fine (i even added in a 5 NPLC)
01 NPLC, 19999samples set 1, sampling 5Hz, autozero=1, filter=0,REL=0 [mean = 0.003uV, SD = 0.488]
01 NPLC, 19999samples set 2, sampling 5Hz, autozero=1, filter=0,REL=0 [mean = 0.019uV, SD = 0.500]
01 NPLC, 19999samples set 3, sampling 5Hz, autozero=1, filter=0,REL=0 [mean = 0.030uV, SD = 0.492]
05 NPLC, 19999samples set 4, sampling 2.5Hz, autozero=1, filter=0,REL=0 [mean = 0.034uV, SD = 0.309]
10 NPLC, 19999samples set 5, sampling 1.5Hz, autozero=1, filter=0,REL=0 [mean = -0.065uV, SD = 0.211]
10 NPLC, 19999samples set 6, sampling 1.5Hz, autozero=1, filter=0,REL=0 [mean = -0.086uV, SD = 0.232]
10 NPLC, 19999samples s14, sampling 1.33Hz, autozero=1, filter=0,REL=0 [mean = 0.017uV, SD = 0.236uV] 1v
10 NPLC, 19999samples s15, sampling 1.33Hz, autozero=1, filter=0,REL=0 [mean = 0.011uV, SD = 0.796uV] 10v
1 NPLC, 19999samples s16, sampling 8Hz, autozero=1, filter=0,REL=0 [mean = -1747uV, SD = 61uV] 100v
1 NPLC, 19999samples s17, sampling 8Hz, autozero=1, filter=0,REL=0 [mean = -1665uV, SD = 197uV] 1000v
when i hit 0.1 NPLC, my noise readings are way way off
0.1 NPLC, 19999samples set 7, sampling 10Hz, autozero=1, filter=0,REL=0 [mean = 1.279uV, SD = 155.668uV !!!! :palm: ]
before this is a recapping run, all caps are replaced with minimum 105oC [5k hrs+++] spec caps, and all have been oversized by at least 1.5x-3x. before the above sets of logs, there are over 50 other logs to track the noise post capping. and so far, as it seems, the mean average is getting lower and lower (the logs are taken in reverse set 7 to set 1, when it all started yesterday, the mean was over -0.5uV, the NPLC 0.1/NPLC0.01 are all gone ape in readings).
curiosity 1) with new caps in place, i have never reached near zero mean before. is my guess correct that larger bypass caps do reduce measurement noise performance?
curiosity 2) when these DMM are switching amongst NPLC modes, does the multislope circuit increase in samplings (and error)? i will try to poke a scope in there, but i have no idea how it works. except for this article http://www.google.com.sg/patents/US5321403 (http://www.google.com.sg/patents/US5321403) ... only barely grasping some bits)
curiosity 3) if i look at the K2000 schematic page 7 on multislope, i am guessing the logic to the left are the different multislope section, goes thru filter around C179, and i am guessing C171 is the key of the entire multislope? the original K2000 schematic is from some chinese guy
curiosity 4) by looking at the noise charted (see pic, Y scale is in uV, yep uV of noise :-DD? this log is 3998 samples, 0.1NPLC, mean = +13.6uV, SD = 166uV ! ouch !), it is as if 1 of the multislope logic to the left is "broken" or injecting noise? i dont suppose anyone have seen such a problem before? in NPLC modes 1 or more, they are all "quiet". from the pic, there seem to be some kind of saturation point @ 250uV. (when i have more time, i will scope this bit of noise)
does anyone have tips on what else could lead to a extremely noisy low NPLC performance?
all input appreciated :P
(edit : added NPLC 10 1v/10v/100v)
-
The NPLC settings of 1 and more (integer) give a rather good (could be 100 dB) suppression of line frequency (and harmonics). So the much higher "noise" at the faster rates is likle coupling to 50/60 Hz or 100/120 Hz ripple. SO to a large extend it is normal to have much more spurious signal with the fast readings. When sampling fast one should be able to see the signal and measure the frequency - so it's not noise but a spurious signal.
Relacing the supply caps with larger values can acutally cause more ripple currents though the ripple voltage at the supply will be lower. So this must not be an improvement. The residual power line coupling can be tricky, as there are several ways of coupling. One might be able to reduce it by carefull fixing the cables at the right position. Possible an extra shielding may be needed. Sometime even reversing the plug (possible in most of europe) has an influence.
-
The NPLC settings of 1 and more (integer) give a rather good (could be 100 dB) suppression of line frequency (and harmonics). So the much higher "noise" at the faster rates is likle coupling to 50/60 Hz or 100/120 Hz ripple. SO to a large extend it is normal to have much more spurious signal with the fast readings. When sampling fast one should be able to see the signal and measure the frequency - so it's not noise but a spurious signal.
Relacing the supply caps with larger values can acutally cause more ripple currents though the ripple voltage at the supply will be lower. So this must not be an improvement. The residual power line coupling can be tricky, as there are several ways of coupling. One might be able to reduce it by carefull fixing the cables at the right position. Possible an extra shielding may be needed. Sometime even reversing the plug (possible in most of europe) has an influence.
yes i did have some thoughts about more problems with higher cap values, maybe i need a 2nd DMM to log the rails and see :P
-
The rippel current from the transformer to the caps will be larger with larger caps - especially the high harmonics. One path of coupling is inductive coupling of these ripple currents. In a poor design also voltage drop on wires / PCB might contribute.
-
i opened up the 2015THD dmm today due to a teething suspicion i have about the noise problem.
i measured the ground or common return paths of regions on the PCB that has a local bypass cap (the usual SMD ceramics). then i discovered that at the furthest point of the supply chain, the ground plane actually have over 0.5ohms :o ... wait a minute, isnt ground planes supporting sensitive circuits suppose to have a good ground to prevent "what do you call this ground resistance errors?"
so after some more checking to make sure it isnt some special inductor thing, i soldered thick jumpers from the main supply bypass common to about 5 locations where ground plane resistances are on a different level. now all planes are under 0.03ohm (but this is measured on a UT61E, with relative zeroed, so it could be higher).
and the following are the 2 plots of "noise"
0002.jpg right off the bat from DMM power on. 1 hour plot, 1v 10NPLC filter/REL=off. AZERO = on
0102.jpg next hour continuation
it looks like big movements even after 2 hours, but on closer scrutiny, using naked eye, the peak to peak noise (looks like under 1uV max) seem to have been reduced by 1/3 or more comparing with my previous plots (looks like 1.5uV).
this is looking to be really interesting, do old used DMM copper ground planes degrade? or isit because of lousy china grade material? or isit because there is material cut back on ground planes used? :-//
(similar to the post before this where i have tried to insert a AC cable common mode inductor --> grey plot, this measurement was done with 1 small 30uH inductor removed. the cable now has only 1 "inductor" 4 turns AC cord on a very high AL-toroid, producing about 280uH)
*update* 2 more logs but in the 2nd the DMM suffered an accidental bump :-DD. as it stands, maybe it is sunday that there are lesser jittery spikes, or it is the effect of removing the parasitic resistance from the ground plane?
next possibility of pushing this to the edge is changing the capacitors again to even lower ESR, and using even heavier gauge ground plane connection jumpers .... cmon neighbors, pls turn on ALL your appliances ! gimme more noise !
-
i made a little progress after adding some SMD bypass caps on suspicion that some had somewhat degraded, using a low grade ESR checker, most of the 100nF caps have a reduced capacity, which suggest further "reforming" or replacement may be in order (http://www.johansondielectrics.com/ceramic-capacitor-aging-made-simple.html (http://www.johansondielectrics.com/ceramic-capacitor-aging-made-simple.html) and here http://www.murata.com/en-sg/support/faqs/products/capacitor/mlcc/char/0006 (http://www.murata.com/en-sg/support/faqs/products/capacitor/mlcc/char/0006) ... learnt something new here abt aging, they are like old batteries !)
1v scale, 10NPLC, 1Hz sampling, AZERO=on, filter/rel = off
average = -0.269uV
skew = -0.059
kurt = -0.123
STDEV = 0.209uV (best of 5 sets = 0.204uV, worse = 0.239uV. compared to initial logs approx 0.5uV)
AVEDEV = 0.168uV
TRIMMEAN 0.1 = 0.998
average STDEV of past 5 hours = 0.21 to 0.24
a casual probe of various points in the analogue section also reveals the multislope section DOES create some noise when it does some kind of charge dump or reset (or maybe that is the actual sampling acquisition burst). there is also a floated part of the circuit where the "ground" is actually 400mV pk-pk of the 50Hz AC
i guess i have to conclude that it is possible to further reduce noise floor, by careful inspection of where to insert additional bypass and "beef up" ground plane. atm, spurious noise still plague the log, the only logical conclusion is noise interference from AC power.
next possible aim is to try to reach 0.1uV noise STDEV once ac noise can be arrested properly :P
-
a long overlay of 5 plots
red - original with some ground plane "beefed" + additional bypass e-caps (mainly around LM399)
grey - same as red + external common mode choke
green - some more additional bypass caps (multislope opamps etc)
pink (right, pink box summary) - different variant of ground plane
black (left, pink box summary) - different variant of ground plane (+ additional SMD bypass) +/- supply lead in. this is the most recent
anomaly A1 to 6 (and aliens) were records where during stable logs (reference to grey/red plot), the plot will skew up wards (or become messy/quiet) leaving NO plots in -ve region. these are suspected to be heavy equipment being turned on elsewhere shifting the AC mains. the events are very visible especially as they last a few seconds. on the other hand there is suspicion of a thermally unstable/noisy component hitting a certain temperature and going apeshiat.
*edit : example blue plot of a relatively stable log suddenly going apeshit
*edit2 : bell curve binning of a short test @ 10v range 10NPLC reveals that the minimum resolving resolution of the DMM is 50nV@10v. it may also suggest resolution is 5nV@1v and 0.5nV for 100mV (which confirms an earlier test at 1v where i increased binning resolution to 1nV, results skip approx every 5th bins). atm improvements in 10v noise are only marginal (small improvement, STDEV 796uV-->755uV), maybe there is something i missed
*edit3 : 100v @ 10NPLC short test. even with the horrible looking skew. the STDEV is nearly half of old logs !
average = -1895uV
skew = -0.92
kurt = +1.13
STDEV = 30.87uV (old data 6 logs average 54uV, alex nitins' log =51uV)
AVEDEV = 23.34uV
TRIMMEAN 0.1 = 0.999
now i cant wait to see what happens after the actual murata SMD caps arrive to replace these china SMD temporary caps
*edit 4 : 100v @ 10NPLC continuation
average = -1869uV
skew = +0.017
kurt = +0.084
STDEV = 19.39uV (new best)
AVEDEV = 15.37uV
TRIMMEAN 0.1 = 0.999
with a curious up drift as if something else has not yet warmed up :-//
*edit 5: a pic of new caps that will be going in for tests. the crap ESR meter cant even read its ESR properly, too bad DE-5000 is not in my to buy list yet. http://sg.rs-online.com/web/p/aluminium-capacitors/7149607P/ (http://sg.rs-online.com/web/p/aluminium-capacitors/7149607P/)
it is so weird, computer motherboards are $100 items, and yet they have better caps than a $1000 DMM
*edit 6: 1000v @ 10NPLC
average = -1802uV
skew = +0.051
kurt = +0.077
STDEV = 80.06uV (old logs average 119uV)
AVEDEV = 63.84uV
TRIMMEAN 0.1 = 1.000
keithley must be thinking these improvements are not worth the extra capacitors, well i agree, it is not like i am driving down noise by 10 fold. but at least now i do know, the situation on the last digit can be improved
-
it looks like i did a little teeny bit more advancement today getting the STDEV just under 0.2uV, by reducing the path resistance L104 is taking to AGND, and introducing a "OSCON" to bypass C227 for testing.
1v scale 10NPLC azero = on (filt/rel = off)
average = 373.74nV
skew = -0.030 /
kurt = +0.106
STDEV = 186.72nV
AVEDEV = 148.37nV
TRIMMEAN 0.1 = 1.001
in the plot, there are 2 very obvious "dips" (around 12000, 14000). which has happened before, this makes me suspect a DC bias problem in my AC mains (https://www.eevblog.com/forum/beginners/are-these-dc-blocker-any-good/ (https://www.eevblog.com/forum/beginners/are-these-dc-blocker-any-good/)). however, without further "logging" my AC supply, i cant know for sure. spot measurements suggests i do not have a DC bias problem, but they always come and go when you do not measure it |O ...
example the plot before this was taken (plot 1347)
average = 387.57nV
skew = -0.062 /
kurt = +0.085
STDEV = 209.22nV
AVEDEV = 165.55nV
TRIMMEAN 0.1 = 1.002
as usual, dips and dips (between 8000-8500 n 9500 onwards). unfortunately, i am nearly out of ideas to find/reduce the effects causing the dips, hopefully something will come to mind soon-ish
a mod idea came to my mind, to use top side IC pins to group common AGND. perhaps next round (as bottom trace variations seems to have been somewhat exhausted) ...
almost rounding up this update post, and plot 1547 is done. and it confirms the under 0.2uV trend, just barely :P
average = 387.64nV
skew = -0.098 /
kurt = +0.122
STDEV = 195.47
AVEDEV = 154.71nV
TRIMMEAN 0.1 = 1.004
as usual, a large dip clearly spoils the nice "picture" @16500
i wonder, if 3458a gets modified ... to read 9 to 9.5 digits consistently ... wouldnt that be awesome?
-
The dips look a little strange, a little like Popcorn noise.
What makes me wonder is, why the average readings are not much close to zero. This usually should be be less than 0.1 µV for a shortet input.
-
yea i am still trying to rule out possibilities to get to the source
i could try to scope around one of these days. but it is so intermittent, i dont think i could hold a probe still for that long :-DD
as for the average, it is because i changed the return path resistances of AGND.
-
I have only one question.
What is this thread doing in beginners section? :) I go this section once in a year (yah, snob detected).
it is so weird, computer motherboards are $100 items, and yet they have better caps than a $1000 DMM
Not really, PC MB's made in hundreds of thousands/month pieces, while bench DMMs few thousands/year?
To be honest, I found evil capacitor theory a bit of a long shot, as they are not charging-discharging frequently, like in switching DC/DCs.
Maybe you sneeze over PCB, making it dirty and leaky? Try careful cleaning with IPA. Also try rear terminals short, it could be bad switch.
You responsible of making me sad again about 2000 I have...
-
@ TiN ... its is suppose to be a random ghetto mod (75% random un-proven ideas)
mmmm switch and rear bananas. maybe i could try that. or even a hard solder short on PCB point to point.
well since i am up and about, i saw some logs done. this 1 really put a smile on my face. its a new best STDEV in 10v scale (under old log 15, that 1 has a STDEV of 795nV)
10v scale 10NPLC azero = on (filt/rel = off), plot 2248
average = 498.27nV
skew = +0.007
kurt = +0.126
STDEV = 550.21nV
AVEDEV = 438.35nV
TRIMMEAN 0.1 = 0.999
plot 2348
average = 565.59nV
skew = -0.015
kurt = +0.008
STDEV = 557.49nV
AVEDEV = 443.86nV
TRIMMEAN 0.1 = 1.000
plot 0048
average = 529.89nV
skew = -0.127
kurt = +0.063
STDEV = 580.67nV
AVEDEV = 461.28nV
TRIMMEAN 0.1 = 1.008
i suppose this nearly adds a 1/4 digit accuracy to 10v scale measurement doesnt it?
taking a peep at plot 0048, it seems when 10v circuit is selected, the dips are more frequent (i realized that i have only 1 old 10v log to compare to, and it is bloody noisy plot), which may suggest, klein's idea of popcorn (semiconductor noise) effect might be true. which could point to a very noisy gain opamp/BJT? :-// ... i think i need a "popcorn" geiger circuit detector !
(right off the bat a huge dip @ 7500 :( )
fyi also the pix of the bottom side (after 3rd wash). 1210 SMD murata replaces old 1206 0.1uF (ESR = 1.6ohm using lousy LCR meter) bypass, but due to space constraint it is stuck on side ways (its a X6S 10uF). on top of that, a giant ecap 470uF 35v. this is the area of L104, the AGND jump wire to "OSCON" bypass. that cap is being piggy backed with the existing smd (its a 3in 1, 0.1uF + 10uF + 330uF). its really asking the 1206 solder pads to do the unthinkable
(and we can see the "bean counter" effect in the plot, the resolution of the DMM here is 50nV)
**update** 2 logs 1kv done, nice numbers as well (new best personal record low STDEV)
plot 0500-58, 1000v scale 10NPLC azero = on (filt/rel = off)
average = -1855.68uV
skew = -0.130
kurt = +0.082
STDEV = 54.55uV SD ppm becomes 0.05 !
AVEDEV = 43.43uV
TRIMMEAN 0.1 = 0.999
(i realize big mistake in previous posts, most xxx.xx readings are suppose to be nV, but i said uV :-DD)
i have a bad tinkering feeling that i am going to satisfy my craving by changing all normal caps to OSCON ... this is not "good" ( i have to blame RS components, the new search GUI is now better than element14, search capacitors by ripple current handling spec!)
-
100v scale 10NPLC azero = on (filt/rel = off), plot 719-00
average = -1803.17nV
skew = +0.057
kurt = -0.030
STDEV = 18.83uV another jackpot !
AVEDEV = 15.14uV
TRIMMEAN 0.1 = 1.000
as a previous post suggested, top side opamp powersupply pin mods. there is also the possibility of opamp swap to low noise version. but being unfamiliar with specific application families, i highlight these 2 based just on noise figures in PDF.
NE5534 -> OPA227 ?
AD711/OPA177-> OPA140 ?
**edit, best 100v plot (1119)
average = -1768.47nV
skew = +0.007
kurt = -0.051
STDEV = 17.96uV
AVEDEV = 14.31uV
TRIMMEAN 0.1 = 1.000
-
I found using histogram frequency distribution more easier to grasp for such noise measurement tasks.
E.g.:
(https://xdevs.com/doc/xDevs.com/dmm_noise/represent_3.png)
-
Without knowing the circuit, it is difficult to impossibel to find OP replacements. It really depends on the way they are used wether the OPs contribute much to the noise and which parameter is important. There often is no easy update that is better in every aspect. Sometime faster is a problem and can make a circuit oscillate or ring more.
There should not be very many (if at all) OPs that give a significant contribution to noise / ripple pick up.
Even with just relacing caps - lower ESR is not allways better. Sometimes ESR is needed to dampen local resonaces at high frequencies. Two low loss caps and a suitable piece of wire can make resonator. One low ESR cap and one with resonable ESR are often the better combination.
For looking at ripple it might be usefull to da a really fast reading, if the DMM supports this. This way one can the the waveform and thus what frequencies (60/120 Hz ?) that contribute. The slower readings are much less sensitive to line synchronous pickup and how much they pick up may depend an phase and can be thus not well repeatable. So one should test for such signal pickup in the fast modes.
-
yes indeed combi caps, it resulted in 1000v 100v 10v 1v having lower noise, but just that 0.1v have slightly more noise (abt 5%). and weird looking ones. i have just finished top trace mod, and is now logging again to see if localized bypass on top side of PCB will help to reduce any further noises.
-
Very interesting experiments 3roomlab!
I would be too worried to experiment like that with my Keithley 2015, as it is my main workhorse multimeter in the lab.
Recently, I've scored 3457A and I'm keen on doing some modifications there to lower the noise and thus make the 7th digit a bit more meaningful.
Your results are very interesting indeed. I always thought that the biggest contributors to noise (at least 1/f or Johnson one) would be 10M resistor divider (for 100/1000V) and JFET + Opamp amplifier with its associated circuitry. I wouldn't suspect the caps, especially common bypass ones.
I was thinking about replacing TL072 in 3457A (used in the JFET amplifier stage) and using a more modern lower noise part, like OPA2134/OPA2192/OPA2140. I still need to analyze how feasible it is and how real improvement it can bring.
I might look at the capacitors and grounding as well.
-
In the 3457 voltage (andohms) input stage, the OP is not critical. Noise is essentially set by the FETs and the series resistors used for protection. The switches in the hybrid might give some contribution (charge injektion from AZ phase and thermal EMF).
Much of the noise could be from 100 K at the input - at least for the white noise this should be more than the FETs. With 1/f noise the JFETs might give more. There may be also noise from the ADC itself. One might be able to check the performance with the resistors shortes out to understand where the noise comes from. This usually the first step before trying to improve a well thought through design. The third important source could be thermal EMF in combination with turbulent air flow. Here some improvement might be posssible. Also HF signals (e.g. wireless phones) might be a significant source of "noise". Looking at the qualitiy of the power supply might in deed help - but this would be more like using the scope. Here modern cap can be better than what was available back then.
So I don't think changing OPs will give an improvement. HP had better OPs than the TL071 to choose, using this OP allready indicates it's not a critical part. Chances are better with OPs that were state of the art at the time of design.
If you really need lower noise in a low level measurement, one likely would need an external amplifier without the need for CAT 2 - 600 V (or similar) protection. Today it is not so difficult to get lower noise, especially if one can tolerate a higher bias and do not need that much of protection. I remember getting lower noise than the 3457 with just an OP07 preamplifier.
-
Very interesting experiments 3roomlab!
I would be too worried to experiment like that with my Keithley 2015, as it is my main workhorse multimeter in the lab.
Recently, I've scored 3457A and I'm keen on doing some modifications there to lower the noise and thus make the 7th digit a bit more meaningful.
Your results are very interesting indeed. I always thought that the biggest contributors to noise (at least 1/f or Johnson one) would be 10M resistor divider (for 100/1000V) and JFET + Opamp amplifier with its associated circuitry. I wouldn't suspect the caps, especially common bypass ones.
I was thinking about replacing TL072 in 3457A (used in the JFET amplifier stage) and using a more modern lower noise part, like OPA2134/OPA2192/OPA2140. I still need to analyze how feasible it is and how real improvement it can bring.
I might look at the capacitors and grounding as well.
i hope you have a good time modding. TBH i was mucking around as i didnt really understand the DMM ( n electronics) that well. for opamp, i think OPA 140/228 looks good, in the keithley 2002 repair thread, TiN mentions AD797 and ADA4627-1. w/o knowing more about the opamps, im not so sure, maybe try all and log some noise? lol
will you post some progression updates? it be interesting to know if it shares similar problems (esp the tiny bypass caps and high trace resistances)
i guess i have to start calling my mods by a date code :-DD, so that i can follow what i myself did
14NovA mod was to FULLY "shorten" AGND path of L104, as i suspected the inductor ringing due to the logics floating on it creates spurious noise. (DMM startup plot 2219). BUT ... @ plot 119, an elephant landed, i have no idea where that dip is from :-//. the plot previous to this is giving STDEV of 0.199uV.
14NovB mod was inversion of 14NovA, remove all AGND "shortening" of L104. at the same time, a few more 10uF bypasses are added on the logic side. (DMM startup plot 0516). as we can see the L104 re-floated does makes monkeys out of the readings (100mV 10 NPLC 1Hz sampling). (logging still in progress)
in the mod before this where 1000/100/10/1v logs have low noise, the AGND shortening was only biased more to the multislope logic ground side (which shares same AGND). however the logic side and the analog section AGND traces are not shortened.
todays log will likely tell the story of which trace shortening i should use on L104 to force lower noise on 100mV range.
**update 2nd hour vs 2nd hour (with aliens landing in plot 616)
*** update as i noticed something strange about the temperature of the chasis going up. i went to measure the DC bias of AC, it is constantly going around 0.05v and AC seem to have slightly dipped (this is likely going to show as anomaly on logs too if i guessed right)
-
In the 3457 voltage (andohms) input stage, the OP is not critical. Noise is essentially set by the FETs and the series resistors used for protection. The switches in the hybrid might give some contribution (charge injektion from AZ phase and thermal EMF).
Much of the noise could be from 100 K at the input - at least for the white noise this should be more than the FETs. With 1/f noise the JFETs might give more. There may be also noise from the ADC itself. One might be able to check the performance with the resistors shortes out to understand where the noise comes from. This usually the first step before trying to improve a well thought through design. The third important source could be thermal EMF in combination with turbulent air flow. Here some improvement might be posssible. Also HF signals (e.g. wireless phones) might be a significant source of "noise". Looking at the qualitiy of the power supply might in deed help - but this would be more like using the scope. Here modern cap can be better than what was available back then.
So I don't think changing OPs will give an improvement. HP had better OPs than the TL071 to choose, using this OP allready indicates it's not a critical part. Chances are better with OPs that were state of the art at the time of design.
If you really need lower noise in a low level measurement, one likely would need an external amplifier without the need for CAT 2 - 600 V (or similar) protection. Today it is not so difficult to get lower noise, especially if one can tolerate a higher bias and do not need that much of protection. I remember getting lower noise than the 3457 with just an OP07 preamplifier.
Thanks for the analysis. To be honest my analog design skills are pretty poor (just simple opamp circuits and single transistors, I do mostly digital or just switching power mosfets on and off for motors :) ), but I think I'm getting infected with volt-nuts disease :)
3457A is pretty old so I thought that there might be more modern low-noise parts nowadays that HP, with all their ingenuity, couldn't use.
What bothers me (and that's why I thought about such mods) is very peculiar ranges arrangement in 3457A. There is no 10V -> 1x amplifier -> ADC path in this instrument. 3V range is the most direct one and even this has 3.33 amplification to bring the signal to 10V levels for the ADC. Next range, 30V, goes through 10M divider (sic!) and is then amplified. This is quite bad, no high input impedance above 3V and likely higher noise. So I thought at least what I can do is to bring this JFET+OpAmp amplifier noise levels a bit lower. I don't want to replace the JFETs because they seem unobtainium. Nobody seems to stock things like LSK389 and similar low noise JFETs (don't remember off hand which ones are in 3457A, but LSK389 is in DMM7510), so I thought about the amplifiers around them. A lot of stuff (resistor networks, analog switches) are in the hybrids so also difficult to mod.
i hope you have a good time modding. TBH i was mucking around as i didnt really understand the DMM ( n electronics) that well. for opamp, i think OPA 140/228 looks good, in the keithley 2002 repair thread, TiN mentions AD797 and ADA4627-1. w/o knowing more about the opamps, im not so sure, maybe try all and log some noise? lol
will you post some progression updates? it be interesting to know if it shares similar problems (esp the tiny bypass caps and high trace resistances)
I'm pretty much the same just mucking around :) I just thought of possible cheap improvements. TiN recently wrote an article about modding 3456A by using triple LM399 to reduce the Vref noise. I could do that as well, but for me it seems already at the point of diminishing returns, not to mention putting LTZ1000 there - got this meter rather cheap. So this input amplifier OpAmp was the only thing I could think of, but maybe I'll play with capacitors as well.
When I get time I'll post some updates. TBH you need a lot of patience for this. Solder a cap, collect 2 hours of data, solder a bit of wire, collect hours of data and so on :)
BTW Do you have any special low thermal shorting plug (these things from Agilent/Keithley are stupidly expensive) or just a bit of copper wire? (3457A has proper binding posts so I often wrap copper solder wick there).
-
haha if i keep on tinkering, i need more than 1 lifetime. atm, i its 24 folders 450+ files, half are bean counter, so over 200+ logs and counting
i didnt have any special shorting plug, i bought some very good banana plug from china. the lantern spring contacts have a nice bulge and spring, it is better than the hirschmanns i bought for 50x the price :(. this then with double 18AWG wire. to offset the thermal coefficient problem (inside hotter than outside), i bunched up some cotton around the shorting plug so that the plug will try to heat up faster than normal and hopefully do lesser EMF voltage. due to the used nature of this unit, i find that every 20-50 plug in-out, the 4mm socket leaves a visible amt of "grounded" socket :-DD. i might want to change this to probably new socket from "multi-contact"
how much are those "official" short plugs?
(3rd hr update plots, 716 modB vs 0019 modA)
-
i didnt have any special shorting plug, i bought some very good banana plug from china. the lantern spring contacts have a nice bulge and spring, it is better than the hirschmanns i bought for 50x the price :(. this then with double 18AWG wire. to offset the thermal coefficient problem (inside hotter than outside), i bunched up some cotton around the shorting plug so that the plug will try to heat up faster than normal and hopefully do lesser EMF voltage. due to the used nature of this unit, i find that every 20-50 plug in-out, the 4mm socket leaves a visible amt of "grounded" socket :-DD. i might want to change this to probably new socket from "multi-contact"
Can you say which ones you got from China? I want to buy some more banana plugs. Most of them are unfortunately gold plated brass, so not great for thermal EMF. For day-to-day cables I don't mind that much and prefer the stacking ones, but for noise and low voltage measurements I thought about buying 4mm dia copper rod, on one side cut through a bit in an X shape to make it more springy, on the other side a small hole to put copper wire and crimp it in the vice. Applying plenty of deoxit everywhere :)
Also I want to try out fork busbars as the source of fork terminals, just need to check binding post diameter:
http://g02.s.alicdn.com/kf/HTB14_UKHpXXXXbQXXXXq6xXFXXXY/202149791/HTB14_UKHpXXXXbQXXXXq6xXFXXXY.jpg (http://g02.s.alicdn.com/kf/HTB14_UKHpXXXXbQXXXXq6xXFXXXY/202149791/HTB14_UKHpXXXXbQXXXXq6xXFXXXY.jpg)
These things look like pure copper, maybe if these are big enough they could be cut into pieces, copper wire crimped somehow and it would make great low-EMF leads.
how much are those "official" short plugs?
Not cheap :)
http://www.tequipment.net/Keithley8610.html (http://www.tequipment.net/Keithley8610.html)
http://www.newark.com/keysight-technologies/34172b/calibration-short-digital-multimeter/dp/92T5065 (http://www.newark.com/keysight-technologies/34172b/calibration-short-digital-multimeter/dp/92T5065)
-
im afraid those i bought are nickel plated brass lol. the plug i soldered is using this.
http://world.taobao.com/item/17014096660.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.28.1KPfKO (http://world.taobao.com/item/17014096660.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.28.1KPfKO)
i also got the gold version to try as well. which has the piggy back socket on the rear of the banana. i have yet to put it into use.
http://world.taobao.com/item/14757565204.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.46.1KPfKO (http://world.taobao.com/item/14757565204.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.46.1KPfKO)
but i find the cotton bunching insulation solves the thermal leak. when using the nickel plated bananas, i did noticed the EMF wrecking ball in my old logs, i kept thinking i needed some special plug too, but i thought if the temperature could be equalized, there would be nearly nothing left to produce disturbing EMF. if the insulation cover is "long" enough so that the temperature leaks in the wire into the outside, the "noisy" temperature difference junction will be no longer at the meeting of 2 different metals and so likely would amount to nearly no EMF (i am assuming alot here) ... but that is my theory and assumption, which seems to have been working well in the newer loggings (or maybe there could be certain artifacts i didnt notice but i wouldnt know)
edit : all serious measurement junctions need a good "mink coat" :-DD, catch a chill and the entire log is fxxxed
the 34172B looks solid ! solid price too !
but for now, i think the $0.05 cotton "coat" kind of enables any contact to any contact
**edit, oh and their J-hook clips are great. they come in "copper" or "gold" plated.
-
I found using histogram frequency distribution more easier to grasp for such noise measurement tasks.
i have these logged too. but atm, i need to see time scale as i need to know when elephant sized artifacts go thru. it is likely the popcorn effect described by kleinstein is the actual cause, as i watch the log, the pops n dips are somewhat always around 1uV in size. also with timescale i could probably estimate if temperature affected the skew in some way
(4th hr comparison update, 816 = modB vs 119 modA)
** for lukier's info, i did this vid sometime ago. you can see the difference in the fin. on the hirschmann, the fin protusion is rather small, so contacts have to be very clean for perfect mating, the china made with somewhat bulgy fins have so far been "harsher" on the socket (i suspect it digged more than it should), but it get good contact (better than the hirschmann i would say 9 out of 10 times, twisting the jack in socket, the hirschmanns will cause the DMM to jump readings more often then the bulgy finned)
https://www.youtube.com/watch?v=HheIqo3PalY (https://www.youtube.com/watch?v=HheIqo3PalY)
while it is bad practise to mate dirty contacts, i find the bulgy finned to be easier to use as there were times, log readings were jumpy due to weak mating.
and this, is the strange trafo hum of my keithley LOL !!! (VFD is off during recording)
https://www.youtube.com/watch?v=EiaR5C0rmi8 (https://www.youtube.com/watch?v=EiaR5C0rmi8)
-
im afraid those i bought are nickel plated brass lol. the plug i soldered is using this.
http://world.taobao.com/item/17014096660.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.28.1KPfKO (http://world.taobao.com/item/17014096660.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.28.1KPfKO)
These are shrouded. Yuck :)
I got these some time ago, not the best and surely not low thermal, but cheap, stackable and with retractable shroud:
http://www.aliexpress.com/item/50pcs-5color-Gold-Plated-Retractable-4mm-Stackable-Plug-Soldering-Type/1781741357.html (http://www.aliexpress.com/item/50pcs-5color-Gold-Plated-Retractable-4mm-Stackable-Plug-Soldering-Type/1781741357.html)
i also got the gold version to try as well. which has the piggy back socket on the rear of the banana. i have yet to put it into use.
http://world.taobao.com/item/14757565204.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.46.1KPfKO (http://world.taobao.com/item/14757565204.htm?fromSite=main&spm=a312a.7700824.w4002-2384870785.46.1KPfKO)
These are 2mm. I have no idea who uses these. 4mm banana seems to be a standard. AFAIR 2mm was sometimes found in very old gear.
but i find the cotton bunching insulation solves the thermal leak. when using the nickel plated bananas, i did noticed the EMF wrecking ball in my old logs, i kept thinking i needed some special plug too, but i thought if the temperature could be equalized, there would be nearly nothing left to produce disturbing EMF. if the insulation cover is "long" enough so that the temperature leaks in the wire into the outside, the "noisy" temperature difference junction will be no longer at the meeting of 2 different metals and so likely would amount to nearly no EMF (i am assuming alot here) ... but that is my theory and assumption, which seems to have been working well in the newer loggings (or maybe there could be certain artifacts i didnt notice but i wouldnt know)
edit : all serious measurement junctions need a good "mink coat" :-DD, catch a chill and the entire log is fxxxed
It seems you are overthinking it. I'm not saying there is something wrong, but double check everything. Nickel shrouded plugs, solder + double wire + cotton. A lot of metal junctions, plastic shrouds insulate a bit, everything has some mass so it takes a while to reach temperature equilibrium etc.
Just get copper wire from UTP cable, clean it and stick it in the sockets. Maybe with some cotton ear buds as TiN often does to keep the wire in place :) + some cover from airflows.
-
Just testung different capacitors in the DMM is tricky: Even if you know about the circuit, it is hard to predict how high frequnency "noise" (more like ringing) on the power supply will change. Its also not clear how signals from the supply influence the result. The caps can also change the amount of electrostatic coupling, as they may work as a lectric shield. As a third effect they can change the thermal effects. So outcome can be rather random: put the DMM to a different place or orinetation and results might be different. If at all one would need to use a good scope to probe the supply, and go for low noise / ringing on the supply first.
With just random tests there is not much to gain.
The OP change in the Keithley that TiN did is more like a lucky find of a minor design flaw. If you have a circuit plan this is sometimes possible, but not every low cost OP is a problem, usually they are the less critical ones. In old times HP used the JFET pairs - they are quite good compared to modern OPs, though the OPA140 comes close in some respect.
With the 3457 I have not seen am obvious weak spot - except for the whole concept of using only a +-3.5 range for the input amplifier, and not having a x 1 setting. So I am afraid there is no easy improvement.
-
@ lukier, sorry abt wrong link, the gold is 4mm stackable (its somewhere in the same web "shop"), see pic
yes i have used the bare copper wire before, but i have trouble in contact consistency, so i changed to those.
-
keep calm and log some more DMM noise !
** update today i did another mod, having the L104 AGND return using a different AGND node. the start up is compared in a 3 in 1 plot (light blue plot #1614), it also came with a huge anomaly near the end lol
red plot uses similar L104 AGND topology but tapping on diff node
magenta is L104 WITHOUT its AGND "shortened"
2nd plot comparison only use the 2 with AGND shortened. black = Nov15 mod, red = Nov 14 mod. the newer mod seem to warm up to more reduction in noise than the previous version.
if 1 were to think of this as a design challenge, you could see it as, how to make limited changes to a noisy circuit which you cannot change the already fabricated PCB design?
-
it is time to reel in the fish nets :popcorn:
6 plots are done by this time. the results are marginally better, but is plague by a new type of noise pattern. all plots are 100mV 10 NPLC @ 1Hz sampling, trafo temp : 47.5oC
plot with the least STDEV (0114)
AVE : 0.514 (uV)
SKW : -0.066
KRT : 0.207
SDV : 0.187
ADV : 0.148
TRM : 1.002
(3 set of plots consistently falls below 0.2uV SD)
the 0.187uV number has been showing up and seem to be the smallest SD limit with the current shoddy ghetto-ish setup. in comparison, alex's SD was 0.19, my own old logs averages around 0.21-0.27.
plot with worse STDEV (0214)
AVE : 0.512
SKW : -0.145
KRT : 1.997
SDV : 0.287
ADV : 0.206
TRM : 1.005
(3 sets are plagued with farty noises :-DD)
as i have observed previously, the noise are always 1uV high, in this case, they are 1uV pk-pk. but the dippy noises are missing in all 6 plots (now i know for sure why kleinstein say it looks like popcorn noise https://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-14-01-00-00-80-75-78/Popcorn-Noise.pdf). there are now "farty" blobs of 1uV p-p stuff, however it could be due to large sample interval, that these are also multiple tiny popcorn noises :popcorn: :popcorn: :popcorn:.
as i looked thru the previous mod, i found some soldering errors. made further changes/corrections (mod 16Nov plot in orange). and did a new log run. 2 temperature sensor are added.
in this mod, multiple 220nF SMD are added on top of the normal bypasses
log start : c156 cluster 27.9C, transformer 27.4C
60min : c156 cluster 44.4C, transformer 40.1C
4th hour
c156 cluster 46.2C, transformer 43.3C
AVE : 302.65nV
SKW : 0.076
KRT : -0.004
SDV : 186.87
ADV : 148.73
TRM : 0.996
-
i return to the "modding-board" today to try a different approach to counter the dippy/peaky/popcorn noise. as observed in many logs, they seem to appear more aggressive over a certain threshold temperature. i dug up a tiny dc fan from a celeron CPU, good old nidec 12v that only consumes 0.06A. i tied this fan to the 7v raw rectified rail (powering the communications), it consumes about 31mA. the small fan is mounted above the cavity of the 2 transformers, it draws air upwards cooling the trafos first, then some air turbulence would circulate thru the rear banana PCB cavity.
in addtion, i wanted to see, what will happen if i removed ALL the major trace "shortening" runs but left L104 and all the modded bypass caps. and this is the warm up plot result (0.1v, 10NPLC, 1.25Hz).
start log- 28.3oC, 1hr - 40.2oC. with active air circulation in place, the temp diff between PCB and trafo is only 0.3oC (compare to last log, PCB area temp after 1hr is 44+)
based on this observation it would be interesting to see what would happen if i use a mini laptop sink blower fan. it could create a large turbulence over the PCB area.
** edit -- i believe i have found the source of the noise. mmbt 3904 / 3906. by using a soldering iron adjusted to 100oC, i was able to heatstress the part and re-create the signature 1uV peak/dips (@100oC, the peak dips go on forever !). but in an attempt to repair it, i think due to my lacking of SMD skills, i may have overstressed the package, and the problem resurfaces :( ... during operation, the 2 particular BJT operates at rather high temperatures of 60+++ oC
edit ** comedy run, after giving the SOT-23 a few taps, i could hear a click. i thought i broke the SOT 23. but it appears the looks more stable now ... o my :P
via further simulation, the 0v buffer section draws direct raw +/-23v dirty DC, using the PNP/NPN pair, supplies constant current of approx 4.5mA to LTC1050 shunted by a series of 6.6v zener. the simulation suggests Q110/Q111 dissipates 100mW. this then calculates to a Tj of approx 100oC+. isnt this too hot for a tiny SOT-23? :(
-
i made some interesting progress today. by temporary modding the zero buffer section with TO92 BJT and adding additional bypass caps. however as it is a try and see test. i only replaced 2x 2N3904 for -ve rail (unfortunately, i used made in china jellybeans as these are what i have at hand, a bunch of BC550C/BC560C are on the way to me, i am lucky to find some in RS components).
PCB air 43.2C, transformer 43.8C, the below stats are from sample 500-4500) 0.1v 10NPLC @1.25Hz
AVE : -0.140uV
SKW : 0.093
KRT : 0.229
SDV : 0.19008, SDV under 0.2 ! YAY !
ADV : 0.14991
TRM : 1.008
( the warm up appears fast due to the gear being already warmed. the best test scenario with SOT23 is so far SDV of 0.179uV, after which heat demon takes over after 2hrs+ and everything goes over 0.2 SDV)
the use of TO-92 appears to be able to circumvent problems encountered with sensitive SOT23 package for now. however when air temperature overshoots 45oC, the 1uV dip/peaks resurfaces. in the TO92 variant, lowering of temperature removes the occurence, in SOT23, the noises persists longer. for TO92, the case temp is measured to be operating approx 10-12oC lower than SOT23 (@200oC/w, which suggests TJ = approx 70-80oC)
there is also a hunch that the zeners (supposedly to regulate LTC1050 supply) are adding some noise? but i do not know for sure atm.
it appears that with better engineering/parts (in this case "tinkering") it could be likely to lower noise even further. if this buffer has a separate flatline DC supply, maybe the resolving power of the DMM could be improved even further? :-//
-
I asume the K2015 follows closely the K2000 schematics:
It's a little supprising to an effect from the small transistors. They are just two constant current supplys to provide the bootstrapped supply for the LTC1050. I would be more afraid of heat from the transistors heating up the OP - this is where the To92 case might be really better, as heat goes to air and not PCB. Still only a minimal difference expected.
A moderate size extra cap (e.g. 10µ Low ESR electrolytic) at the LTC1050 supply might give a minimal improvement, but don't expect much.
Much of the noise is likely just the noise from the LTC1050 itself and a little from the following stage. So not much improvements expected from the supply.
Though old the LTC1050 is still a good quality auto zero OP with low bias current. Its easy to find lower noise ones, but they usually have too much bias.
-
i tried to simulate the setup. injecting a 10mV AC as virtual trafo ripple. it seems approx 100uV of noise could still make it to the 1050. as the entire 1050 circuit then floats on also a negative constant current, it is likely the output is also a float relative to the noise (on -ve rail?). its alot of variables im not sure of, so ima just change bitsy pieces and log and observe.
on a side note, i wonder how did keithley get to have the SOT23 behave so well. did they resort to binning the 3904/3906? if so, at our end, what could we do to bin such common parts :-DD :-//. in scouring the pdfs, there are only so few low noise BJT to swap around n "play" this portion.
**note that for that last log, i still have a small fan inside moving the air "slowly"
-
I don't see higher demands on the small (SOT23) transistors for the current sources. The ones that get hot are not critical at all (they just need to deliver power), and the ones that set the current don't get really hot. Also noise should not be critical, as the current sources work against the output of the coarse buffer OP - so the voltage is set by the OP, that just needs to drive the difference in currents (not critical) and the output current of the 1050. Even low qualitiy jelly been NPN/PNPs should give a resonable higher impedance current source.
I don't know how good the model for the LTC1050 is, but i don't think PSRR should be so poor at 100/120 Hz. I would not expect much noise/ripple at the OPs supply - just noise form the OP driving the supply and the noise from the zener diodes. Here keithly might have tested the OPs to find some with at least typical performance (low Bias).
The LTC1050 would be a candidate for an OP upgrade if you really want to get significant better - though this likely would mean using a lower noise type and selecting lower than typical bias (e.g. 1 out of 10). Modern OPs are not that much better than the LTC1050, but bias currents a parameter where binning might help.
-
:-DD well, i dont think i have enough tech and knowledge on my hands to bin things properly at this stage. i read an interesting article about 1/f noise by Vojt?ch Janásek (http://www.janascard.cz/PDF/Design%20of%20ultra%20low%20noise%20amplifiers.pdf (http://www.janascard.cz/PDF/Design%20of%20ultra%20low%20noise%20amplifiers.pdf)), it made me want to find out more about lower noise BJT to the extend to wanting to measure 1/f noise. maybe in this instance, ability to measure which node has most 1/f noise could help :-//. but that would mean making something with really low low noise. arrgh need more (low noise) gear to enable more (low noise) gear, chicken and egg problem lol
the interesting thing in his article is about parralleling BJT to achieve even lower noise. which is financially viable since parrallel LTC1050 opamp (or other low noise) would cost a crazy amount if in order to somewhat bin a stock of op amp or other BJT
some interesting update
2nd hr
AVE : -0.37uV
SKW : -0.126
KRT : 0.067
SDV : 0.214 (o no!)
ADV : 0.170
TRM : 0.995
( each hr, the SDV reduces about 0.01 -- 0.188, 0.174)
5th hr (trafo temp 43.5C) plot 0415
AVE : -0.61uV
SKW : 0.0002 (<--- nearly a straight line)
KRT : 0.0158
SDV : 0.1689 (new low!)
ADV : 0.1345
TRM : 1.0000
addon** 6th hr looking good too
AVE : -0.60uV
SKW : 0.043
KRT : 0.081
SDV : 0.1761
ADV : 0.139
TRM : 1.0007
i think i will keep this running to see how far will the stability last lol
-
Vojtech Janasek's papers are quite interesting. I want to build his variant of Wien bridge oscillator at some point (140 dB THD!).
Want to measure low noise? This might be helpful:
https://www.eevblog.com/forum/projects/low-frequency-very-low-level-dc-biased-noise-measurements/ (https://www.eevblog.com/forum/projects/low-frequency-very-low-level-dc-biased-noise-measurements/)
and of course Jim Williams' classic, AN124 from Linear.
In general it is quite tricky. Expensive or preselected capacitors, plenty of shielding, careful power distribution (avoid ground loops, batteries), low noise JFETs and a lot of patience etc.
Once I wondered if I could measure noise with my lock-in amplifier, it has 6nV/sqrt(Hz) input noise and plenty of dynamic range. But then I would have to modulate the DC signal of interest with lock-in reference output (e.g. switching voltage reference on/off with a transistor) but then I suppose the switch circuitry would produce more noise then the DUT.
-
in the thread there is something very interesting about the eneloop plot post#65 by andreas. 0.1uV p-p noise only ! wow ? i wonder what if its LIFEPO4. and then power the DMM off this low noise DC pack.
update** now that ppl are starting to wake up ... burst noise is also appearing in the logs. but unlike previous logs, log 0615 still holds under 0.2 SDV.
-
The amplifier needs to have low voltage noise, low current noise and a low bias. Usually low current noise also means now bias.
It's rather easy to find OPs that are better in either voltage or current noise, but difficult to get both in one amplifier. BJT OPs usually (eccept LT1012 or similar, which have too much voltage noise) have way to much current noise. As there is a 100 K resistor (or the impedance of the divider) or so at the input, a 1 pA noise current is equivalent to 100 nV of noise. So BJT OPs are practically not an option, despite of the low voltage noise. There can be additional current noise from leakage currents, even if they compensate - so a clean board is important.
Also because of drift, the input essentially needs to be a Auto Zero OP like the LTC1050. Though old this is still a good type for this purpose. Having two of the LTC1050 in parallel increases noise and bias current - so this may no be better overall.
If you really need low noise there may be no way around an amplifier that is adapted to the specific signal source. For low impedance sources one can use a an amplifier with low voltage noise, but higher current noise. This may not need so excotic components. This might also need an adapted overvoltage protection. So usually an external amplifier is needed, close to the signal source. The DMM than only needs to have low noise in the 10 V range where it works best.
-
what is your opinon of ADA4638 powered @ 10v. the spec have some interesting numbers. it doesnt seem like a widely used opamp (maybe the 10Hz noise is terrible haha)
-
The ADA4638 is a AZ OP und thus has essentially no 1/f noise.
The trouble is, that it has quite some bias current (40 pA typical) - thats a little high for a DMM input.
Noise is only slightly better than the LTC1050 (1.2 µVpp vs. 1.6 µVpp for 0.1-10 Hz).
The AD8638 would be similar in bias to the LTC1050 und lower noise (1.2 µV with 1.5 pA typical bias).
The rather comon AD8551 is also quite good (1 µVpp with 10 pA (typical) bias),
It's 5 V only , but this is not a big problem in the bootstrapped configuration.
Another low noise, but rather high bias option would be the AD8628, at 0.5 µVpp and 30 pA bias.
But keep in mind there are also other soures of noise, like the resistors itself and the following stage which should give something like 0.7µVpp of noise if based on OP177.
It should be resonable easy to check how much noise comes from the stages past the input buffer stage: current measurements start essentially from there. So one should compare the noise in voltage (e.g. 0.1 V range) with the current mode noise.
-
i guess if i cant cure my "itch", i might just opt to start trying opamp swaps lol
i recieved my package of BC550C/BC560C today and replaced all the NPN/PNP BJT. the plot is much quieter now, BUT A STRANGE ITCH TELLS ME, it is still not quiet enough :-DD (after seeing robrenz 152hr log SDV of 0.076uV !!! on his tektronix 4050 !!! WOT ?? )
the front end of the plot is just coming out of a warm up, and same as before internally there is a small circulator fan.
AVE : -2.21uV (internal air temp 41.5oC)
SKW : 0.035
KRT : -0.014
SDV : 0.166 (sample 500-3600)
ADV : 0.132 (sample 500-3600)
TRM : 1.001
it also appears, this is equivalent to 1 of the 2N39xx logs with partial TO92 mod
anybody have even lower noise BJT to recommend? :P
-
If the 166 nV Std. are for 10 NPLC setting this is allready rather close to the nominal noise of the LTC1050. Noise Bandwith is 2.5 Hz and thus the 166nV Std means about 100 nV/Sqrt(Hz) of noise in case of white noise. This not much more than the 90 nV/Sqrt(Hz) specified for the LTC1050.
The plan also has other noise soures, like a 20 K resistor that gives about 15 nV/Sqrt(Hz) and the OPA177 in the gain stage which might give a similar noise contribution.
It's no suprise to see not much difference between the diffrent transistors in the current sources - the 2 ones that get hot not even have much influence on the current. Noise from the current sources should be hardly detectable at the output. It's more likely a thermal effect that is possible from the small SOT23 transistors.
-
i see, i dont quite understand the calculation, how does 1 do the conversion from PDF spec nV/sqrt(Hz) to compare the SDV? if 10NPLC approximates to 100nV/sqrt(hz), how do we translate robrenz's tek4050 (73nV SDV)?
i think i caught a glimpse of his SDV in the LTZ1000 or was it the LM399 discussion thread. found it (https://www.eevblog.com/forum/testgear/tektronix-dmm-4050-shows-exceptionally-good-performance/msg388153/#msg388153 (https://www.eevblog.com/forum/testgear/tektronix-dmm-4050-shows-exceptionally-good-performance/msg388153/#msg388153)), is the lower noise record due to 100NPLC?
since a few hours have gone by, there is some logs in the bag. originally the intent of the mini fan inside was to circulate air and reduce some temperature, but now as i have converted fully to TO-92 BJT, i thought i log some w/o fan working. and it came out even better. no pops and sizzles ! yum yum !
i will just copy the XLS result as is, the numbers are arranged as follows
AVERAGE | | STDEV (in nV) all plots are 100mV scale 10NPLC, AZERO on. manual REL +2uV
SKEW | | AVEDEV
KURT | | TRIMMEAN
plot 0204
-324.7052777778 526.0146096479
-0.1100208528 525.8307811728
-0.799885848 1.0006576714
plot 0304
-1470.1225 157.6810638436
0.1302137461 125.8797902778
0.178574312 1.0009115936
plot 0404
-1402.9163888889 179.471967593
0.1201923798 158.0596367284
-0.2535748744 1.0012086594
plot 0504
-1141.2641666667 153.2140025044
0.005902222 123.2643449074
0.2425810864 1.0002417992
plot 0604
-1085.2594444445 153.3506986219
0.0867791975 122.6290722222
-0.0720036643 1.0008171796
plot 0704
-1128.9155555556 155.5941890996
0.0283555016 123.0794123457
-0.0130345579 1.0000723408
*edit : i should also add that the FLIR-ed temperature of the BC5xx BJT is approx 41oC. that is way way under the 61-65oC of the SOT23 BJT packages. i also need to mention that the bootstrapped current regulator resistor has been modded also to a higher value of 172ohms from 150ohms, a reduction of approx 0.5mA
final PCB air temperature 43.2oC, trafo temp 42.8oC
hmmm another 50nV to shave off perhaps :-DD ... well this is getting exciting >:D
(come to think of it, all along i had the wrong impression that the noise came from my dirty AC mains, and i have not added the large 100mH filter yet)
-
i see, i dont quite understand the calculation, how does 1 do the conversion from PDF spec nV/sqrt(Hz) to compare the SDV? if 10NPLC approximates to 100nV/sqrt(hz), how do we translate robrenz's tek4050 (73nV SDV)? i think i caught a glimpse of his SDV in the LTZ1000 or was it the LM399 discussion thread. found it (https://www.eevblog.com/forum/testgear/tektronix-dmm-4050-shows-exceptionally-good-performance/msg388153/#msg388153 (https://www.eevblog.com/forum/testgear/tektronix-dmm-4050-shows-exceptionally-good-performance/msg388153/#msg388153)), is the lower noise record due to 100NPLC?
It is probably due to 100 NPLC. Today I was playing a bit with my 3457A and after a long warm up, on the 30 mV range, with 10 measurements (NPLC 100, NRDGS 10, single trigger, MATH STAT) I got around 40-50 nV std. dev. With 10 NPLC ~120, with 1 NPLC 400-500 AFAIR.
However this was only 10 samples = 20 s. I doubt I could get Robrenz's 73 nV over 152 hours. Not even due to the multimeter itself, but my lab has uncontrolled temperature and way too much switchmode gear always on, therefore RF interference unstable mains I suppose.
-
hmmm 100NPLC, @lukier do you have plans to put a AC isolation transformer to counter some AC noise? or maybe common mode filter etc?
my DMM is running next to a bunch of PCs, so i think there is still noisy AC here
-
hmmm 100NPLC, @lukier do you have plans to put a AC isolation transformer to counter some AC noise? or maybe common mode filter etc?
Not anytime soon. It is hard to find nice shielded medical grade ones on ebay (in the EU at least, and these things are heavy) and I'm not sure about the builders variety (called site transformer), a lot of them have 110V secondary, don't know why, seems useless in the EU.
Should get one at some point, or a HV differential probe, because recently I almost fried my DS1054Z by careless probing around SMPS. Fortunately RCD + fuse switched the power off quickly and even the probe survived.
-
If the 166 nV Std. are for 10 NPLC setting this is allready rather close to the nominal noise of the LTC1050. Noise Bandwith is 2.5 Hz and thus the 166nV Std means about 100 nV/Sqrt(Hz) of noise in case of white noise. This not much more than the 90 nV/Sqrt(Hz) specified for the LTC1050.
The plan also has other noise soures, like a 20 K resistor that gives about 15 nV/Sqrt(Hz) and the OPA177 in the gain stage which might give a similar noise contribution.
It's no suprise to see not much difference between the diffrent transistors in the current sources - the 2 ones that get hot not even have much influence on the current. Noise from the current sources should be hardly detectable at the output. It's more likely a thermal effect that is possible from the small SOT23 transistors.
noob question. how do i derive 100nV noise from 2.5Hz bandwidth and how do i know it has to be 2.5Hz? 10NPLC in my mind seems like "averaging" of 10 power cycles, is this how all NPLCs work in general? like a form of averaging?
to add on some more plots to verify under 160nV plots, i guess this is really the practical limits of the currrent mods (capacitors + TO92 BJT)
plot 2030 : SDV 153nV (0.1v scale 10 NPLC, REL : manual, 3600 samples, 1 sample/sec)
plot 2130 : SDV 156nV
this run is taken without circulator fan (running air temp 44oC), there was a previous test run with circulator fan running on the raw 7v rail, it produced about 3nV extra noise (strangely low, notable but seems beyond reliable resolving power of the DMM, but wait should it be considered?), running air temp was approx 41oC. this run is done setting up in another room w/o any electrical appliances, but it seems no different from being logged in the "noisy" room :P (same AC power phase in any case). i do suspect there is some amount of thermal EMF noise in it, but i have no idea how to verify that component :( (or more importantly, to remove it ! >:D pls feel free to give me ideas to try :P )
-
noob question. how do i derive 100nV noise from 2.5Hz bandwidth and how do i know it has to be 2.5Hz? 10NPLC in my mind seems like "averaging" of 10 power cycles, is this how all NPLCs work in general? like a form of averaging?
I too think that higher NPLC is sort of equivalent to averaging, but I stand to be corrected what is exact difference. I suppose higher CMRR with higher NPLC and the averaging there happens in the integrator of the multi-slope converter, thus slightly before being converted to the digital form. Averaging ADC readings might produce slightly different results due to limited numerical precision and quantization I suppose. Also this NPLC business assumes Gaussian nature of the noise if I'm not mistaken.
Keithley 2001 and 2002 have synchronous autozero, so I suppose it senses AC mains with zero crossing to synchronize ADC operation in a precise manner.
-
I agree with lukier on how the NPLC / averaging works. Depending on the DMM, higher NPLC settings may actually use averaging.
So it is expected to see the noise (e.g. STD value) go down with about the square root of the number of PLC. At very slow measurements drift and 1/f noise can make the noise higher than expected. But at least the noise from the LTC1050 has essentially no 1/f noise.
At 10 NPLC the signal is integrated of 10 cycles or 1/5 s. This gives an effective Bandwidth of 2,5 Hz - assuming white noise and no extra filtering.
Using an integer number of power line cycles gives a very good suppresion the power line coupling. So there measurements are hardly sensitive to coupling from the transformer or similar. Things can get very different for the faster than one power cycle - these measurements might resolve the coupled signal and thus can give much higher RMS values.
For AC suppresion the timing does not need to be really syncronized to zero crossing - coupling can produce phase shifts and thus it is not clear how the phase of the signal coupled to the input is.
The best way to get really low noise, is to use a seprarate external amplifier and use the DMM in the 10 V range. There are AZ OPs available at 1/15 the noise of the LTC1050, but these have to much bias to be used as an universal amplifier in a DMM. Also the protection circuit might produce more noise.
-
i was trying out combinations of NPLC + averaging to emulate NPLC 100.
it seems i may have hit a good spot. it comes close to robrenz 0.073 uV, big big assumption here of using his SDV as a guideline for 100NPLC, and assuming this "moving averages" behaves similarly to NPLC method of reducing "noise" (or extending NPLC "range")
i think i finally understand how to use NPLC + MOV combination to extent the K2015 physical measurement limits. NPLC + MOV measurement bandwidth has to coincide with FETCH sampling rate (or at least sampling rate has to be slower). over-lapping of each sample will result in weird plots.
using NPLC10 + MOV6.@1.1Hz gives 90nV (SDV) <-- weird plot 0214
using NPLC10 + MOV5 @1Hz gives 79.20nV (SDV) plot 0505 <-- equiv of NPLC 50?
using NPLC10 + MOV4 @1.25Hz gives 92.05nV (SDV) plot 0838 <-- equiv of NPLC 40?
using NPLC10 + MOV6 @0.83Hz gives 73.67 nV (SDV) <-- equiv of NPLC 60?
using NPLC10 + MOV10 @0.5Hz gives 58.86nV (SDV) <-- equiv of NPLC 100?
REP averaging appears to be a totally different beast than MOV averaging. and the timebase is totally different. i think REP averaging is the correct method to extend NPLC as it takes averaging from X number of samples w/o regard for previous averaged value. however, it seems the limited processing inside K2015 requires about 3.3x more total sampling time.
1) using NPLC10 + REP5 @0.3Hz gives SDV 84.61nV <-- NPLC 50?
2) using NPLC10 + REP10 @6.6sec/sample gives SDV 63.15nV <-- NPLC 100? (136 samples)
3) using NPLC10 + REP10 @6.6sec/sample gives SDV 61.08nV <-- NPLC 100? (another 136 samples)
i am guessing NPLC10+REP100 will take 66seconds to process 1 sample >:D giving NPLC 1000 ! this is the reason why scientists need chinese elixir of long life, not enough time to collect samples !
mathematically speaking, if 6 averages of NPLC10 is equivalent of NPLC60, it would mean 100 averages would make the K2015 capable of NPLC 1000?
i think i am somewhat convinced that NPLC 1000 is quite possible and it could collect valid NPLC 1000 data. is my conclusion logical?
-
3458A's manual state that NPLC over 10 are average of number of NPLC10 samples. Might not apply to K2000 though. K2002 have NPLC up to 50, but I barely ever see any big difference between 50 and 10.
I had 2001 in works to replace LM399 with LTZ, but it's not working right (oscillates like crazy :)) yet.
-
3458A's manual state that NPLC over 10 are average of number of NPLC10 samples. Might not apply to K2000 though. K2002 have NPLC up to 50, but I barely ever see any big difference between 50 and 10.
I had 2001 in works to replace LM399 with LTZ, but it's not working right (oscillates like crazy :)) yet.
hmmm i assume, if all normal electronic noise are quite similar, giving similar bell curve w/o much introduction of external noises. in theory, the same math should be applicable? it is all basically sum and average, and then summed and average (probably with increased bits of error, and more samples reduces or makes the error more visible)
r u not using your spare LTZ in it? the 2001?
edit** ok now i guess i know why max NPLC for K2015 is 10, i suppose K20xx design is based around a similar framework of many popular bench DMMs of how to handle NPLC. your information about how 3458a handles NPLC 10 pretty much nails it that "REPeating average" can "multiply" its base NPLC10 to NPLC 1000 :P
-
I did use my module, but 2001 have not simple way of reference driving, it's part of few other reference generation driving on ADC module, so need debug it a bit more, to understand how it works.
Simple "remove LM399, pop +7V from LTZ" did not work. I posted about it in 2001 thread some time ago. Anyway, it's offtopic here. Upgrading 2000 with LTZ should be much simpler job, but I'm not going to do that. :)
-
hmmm zero experience with 2001, i would need to tinker to know more (my electronics theory is terribad). maybe it have the same SOT23 BJT problem?
**edit. attached pic, showing the extent of the PCB topside mods. it looks quite hideous, flux "pee" all over :-DD and not very orthodox, hope it can give some ideas for other tinkerers. ceramic SMD caps used are 1210 (esp bottom side), for lower ESR. the first noticeable noise improvement are from them 10uF replacing the 0.1uF (see pic in post #16). topside most noticeable improvement was reduction of generic popcorn noise (identified by kleinstein) which came out of the SOT23. sidenote : the 1206 10uF bypasses added do not seem to give big noise improvements, but they are left there anyway.
** edit 2 : testing NPLC 100 logging (plot 1722) total 19hrs
STDEV 73.79nV.
SKEW -0.2006
KURT 0.6328 (lotsa fluctuations !)
18hrs voltage drift from 1st hour mean is -3nV
total known DMM internal temp change 0.2oC
being new to the world of NPLC 100, a XY plot shows me all the crap parts of the log clearly. NPLC100 sensitivity makes NPLC 10 looks like a 3.5digit DMM. and i clearly need a good AC isolation device as tiny fluctuations can cause big changes in long term readings :P and make a few days worth of log go to waste
quietest 1hr block of 100NPLC (of the 19 hrs logged)
STDEV 60.38nV
SKEW -0.0231
KURT 0.0490
-
with the new understanding that "REPeating average" function can be used as a NPLC multiplier. today i try this DMM ability in a way to compare with the new known noise characteristics of the modded K2015 @0.1v range (SDV about 155nV @ NPLC 10)
the results is quite astonishing :P (or at least to me). due to the shorter NPLC cycle, i could also sample at a higher rate of 2Hz :
[NPLC1*10REP], 100mV. sampling 2Hz. azero = on (7200samples/hr) + REL adjusted in xls sheet
SKEW -0.080
KURT -0.174
STDEV 151.49nV
TRIMMEAN 1.002
even with a skewed start-up into a stable plot, the SDV obtained beats my usual 155nV. this may mean a 1NPLC * 100REP may even beat my last 100NPLC plot test plot (which means instead of using 6.6seconds delay done in the test run, on 1NPLC*100REP, it would take about 2.6seconds)
-
With 1 NPLC Bandwidth should be 25 Hz. Noise goes up with the square root of the bandwidth and down with the square root of the number of samples for areraging. So there is no big difference between using a longer time for each conversion or more averaging. The only difference is doing averaging analog or digital - so no supprise to see no real difference.
The overall data rate might be different because auto zero also takes some extra time for switching.
Things can get a little different if there is drift or noise that is stronger at low frequencies. Than going from 10 NPLC to 100 NPL may give less reduction and the repeated autozero may also make a difference. However here the main noise source is essentially white noise from the LTC1050.
-
a little more improvement again. with some bulky heatsink mods. this reduces the internal air temp to 41.9oC (without using any fan circulator). and the DMM is now having to "stand" on its side upright (with the orientation of the banana jacks below). the large heatsink are glued to almost the entire bottom side (which is now vertical, which becomes a large radiator of sorts)
this produces the 0052-44 plot. [2NPLC*5REP] 0.1v scale @ 1.5Hz, 5400samples/hr (azero=on, manual REL)
STDEV = 144.56nV, SKEW= -0.024, KURT=0.166, TRIMMEAN= 0.999
first time ever breaching 0.15 barrier. in a previous test run, 1NPLC*10REP produces a plot with about 160nV SDV.
-
Remember that LM399 is sensitive to orientation :) Adding some extra insulation might help the internal header do its job.
-
and so ...
the itch returns ...
why does 10v range have so high a pk-pk noise?
dont turn it on ... take it apart !
and back to square 1, step by step tweak and log more noise ...
in order to reliably improve usability of last digit, i feel that % error of 90day PPM drift/error margin should not be exceeded by more than 20%.
this means that 0.1v and 100v ranges always fail this criteria. except for 1 special log 0.1v @ 100NPLC, dropping down to only 8.9% ...
but all these are now history as the PCB is yet again tweaked, new logs are on the order for next few days ...
edit * minor changes are done to the DMM again. in this round i took some time to look at front and rear disparity in readings, which has quite a difference. which could mean a problem in the switch, or it could be the socket, o boy
0.1v 1NPLC test run, STDEV 0.46uV, pp noise 3.36uV. PPM range 4.6, pp noise PPM 33.6
@1NPLC if we treat this as the base noise (w/o averaging to 10NPLC), this could be a better representation of what noise i am trying to solve in the machine ... maybe :P
edit ** due to a lack of low thermal EMF connectivity parts on hand, in this next minor mod, i solder a jump cable to short the sense HI-LO. this bypasses the switch, banana and internal cable interconnects. in a short looky look, the 2w ohm indicates front/rear ohms as being compensated internally for approx -0.07ohm/-0.1ohm respectively. now we shall go back to logging this variant. (short note : the LO is connected to AGND as well, while HI i used a leg of R113. this log will probably tell, how much thermal noise the front end connection has hopefully
-
and yes ... i made some more improvements again. and again, in a area which should not seem to influence final noise. but it did :-//
as with the previous looky looky poking around, i had some thoughts that the zener (VR107/108) was a trouble maker. i had some spare zener (panasonic DZ2J series, 4.7v. SOD323, approx Tja = 250oC). the est current thru the zener is about 4-5mA, power dissipation is approx 0.025w, = Trise of abt 6C
based on the last 3600-7200 samples of plot 2213 (this is a 2Hz plot 7.2k samples), we are looking at 1NPLC plot (yes the super noisy ones), we have a STDEV = 0.392nV (with stock SOT23 zener, STDEV was average 0.45-0.5uV BUT for a flat 3600 sample plot). i thought shit, 7 year old zener, must be noisy as crap!
and the MAX-MIN p-p noise is now 2.9uV as opposed to average over 3.4uV
these cheap SOT23 zeners are suppose to provide 5v to the LTC1050 zero buffer opamp, they are changed now to 9.3v using 2x 4.7v.
come to think of it, there are 2 more 6v SOT23 zener at the LM399, they are suppose to be giving +/- 14v VREF. what the heck !?!?
so maybe i should get some 5v VREF zener (LM336?LM329?) and further enhance the zero buffer. but what should i replace the 6.2v with? there arent any VREF 6.2v zeners. :-// ... 1n829 ?
( if the noise of the 1NPLC is reduced more, it will look like a 10NPLC plot, when i first logged w/o any mods. it would be hilarious if NPLC1 has same noise profile as NPLC10)
*** i guess i was tired, and was poking at the DMM and shorted something. now its not happy with me :( ... mod -> becomes repair :(
-
as i was going thru this circuit (VREF section of K2015), the workings of how it manage to bump the LM399 into both a + and - 14 volts just doesnt come to me. i cant seem to visualize which resistor is being used to 2x gain the opamps? (or maybe i lack of sleep again)
-
This circuit part is still relatively easy:
U139 is producing the positive voltages and U140 is producing the negative ones.
The transistors zener diode are just there to extend the output range and reduce the power disipation of the OPS.
The inverting input of U140 is a virtual ground - so the positve side divider works towards this virtual ground, not real GND. Besides saving one high qualitiy resisitor this alows sensing GND with a low current line. So it's a rather clever circuit.
p.s. The resistors A4 ... A14 are not part of creating the ref voltages, but likely part of the ADC or amplification before it.
-
ok let me try to understand
so U139 pin 6 current drains so that current thru Q130+VR113+A1+A2 show a voltage on pin 2 to equalizes with pin 3 (LM399 VREF)
then on the flip side U140 pin 6 current sources so that VR112+Q129+A4 equalizes virtual zero pin 2 to actual zero pin 3? but because pin3 is a float, does it mean U140 is the key of pivoting both +/-14v around the virtual zero? (so A1/2/3 balances a "see-saw" with A4? so if resistor value drifts, the balance skews? so it relies alot more on the A1/2/3/4 character for stability?)
thanks for deciphering :P
on a side note, R315 seems of no use, wouldnt that add noise?
-
The relative stability of the resistors is critical - this is why they are in an array to have close matching TC and similar drift.
The positive +14 V output scales with (A1+A2+A3) / A3. The -14 V reference scales with A4/A3. So they depend on the resistor reatios, but not more than needed.
R315 is needed for startup. Initailly the +14 v is still at zero as it is derived from the reference. So there is a little current needed to bring up the reference so that the ref output can than deliver more current. It is not that much current comming from there, so the influence is small. There is no significant noise coming from R315 - if at all it gives a slight dependence of the reference voltage on the +15 V supply. But at about 1 Ohm of output impedance of the LM399 and 100 K for R315 this is only a very small fraction of the supply that enters. There would have been ways to avoid this, but it's nothing to worry about.
-
:palm: ah i get it now
matching the resistors exactly will be a tough nut to crack
-
Yes one scale the reference circuit to higher voltages if one wants to. However if it is to drive possibly capacitive loads, a modified version, more like a small pwer supply is probably better.
-
with slightly more understanding of what is going on with the VREF section, i wanted to try to simulate and find out what possible noise source dominates the section. after several iterations of simulations, i think these few pics give a close example of what is happening (probably)
pic5- knowing pin6 is driving @ 8.9v, we replace the zener to be represented by a resistor (there seems to be some problem with simulated zener). so we derive R1 noise to be possibly 40uV. dominant noise is from VREF
pic6- by subjecting pin3 to a LPF (VREF feed), we get a lower noise, and a mix of noise from all sources.
pic7- it appear R10/R9 need to go ape to get really low noise, and it may be possible to replace 6v2 zener with actually a resistor.
unknowns : reduction in VREF noise mean reduction in DMM reading uncertainty? (especially w/o intervention of NPLC/averaging).
-
The dominant noise source is likely the reference chip (LM399). So don't expect to much from reducing the noise of amplifier.
There will be a littel bit of noise from the 6.2 V zener used for level shifting, but here the OP will compensate for most of it, especially the lower frequency part. A capacitor (e.g. 1 µF) in parallel to the 6.2 zener could reduce the higher frequency noise, where the OP may not be as effective in compensating it. Alternatively 2 or 3 LEDs in series might be an lower noise alternative to the zener (no stable voltage is needed, just about 4-12 volts). Just a resistor and capacitor in parallel might work to. Without the capacitor it might be to slow and PSSR will be not that good.
Filtering of the reference might reduce higher frequency noise (e.g. >100 Hz). This might help a little at the short integration times (1 PLC), but less to nothing at long integration times. It is just very difficult to filter out low frequencies.
-
The dominant noise source is likely the reference chip (LM399). So don't expect to much from reducing the noise of amplifier.
There will be a littel bit of noise from the 6.2 V zener used for level shifting, but here the OP will compensate for most of it, especially the lower frequency part. A capacitor (e.g. 1 µF) in parallel to the 6.2 zener could reduce the higher frequency noise, where the OP may not be as effective in compensating it. Alternatively 2 or 3 LEDs in series might be an lower noise alternative to the zener (no stable voltage is needed, just about 4-12 volts). Just a resistor and capacitor in parallel might work to. Without the capacitor it might be to slow and PSSR will be not that good.
Filtering of the reference might reduce higher frequency noise (e.g. >100 Hz). This might help a little at the short integration times (1 PLC), but less to nothing at long integration times. It is just very difficult to filter out low frequencies.
hmmm ok i will try LED once i get parts to revive the DMM
** edit .. interesting question: did anyone characterize their drift? lol
-
The zener diode is only there to shift the ouput range of the OP, to get the 14.x V output range. So drft of zener diode or a replacement would not matter at all - anything in the 3-20 V range should work. Just the noise of a typical zener diode may not be optimal.
LEDs forward voltage is temperature dependent, similar to normal diodes. There is also a good chance to see some drift towards lower voltage as the LED ages and more non radiative recombination paths slowly get added. So a LED won't be long time stable.
-
With noise it does not hep very much if you reduce the small contributions to overall noise even further. At least in the 100 mV and likely also in the 1 V range the main contribution to the DMM's noise is the input buffering amplifier (LTC1050). So even if all other nosie source would be eliminated you can only expect something like 10% less noise.
In the few cases one needs to measure a small low noise DC voltage, I would consider an extra external preamplifier. Especially if you can live with a lower CAT rating, noise can be much smaller (e.g. a factor of 10 or 20). With modern AZ OPs this is not that difficult any more.
-
power sub-board is running. somewhat too cool it seems (iirc old stock heatsinks run at approx 53C?)
+5V A/D rail, +8.61v in, +4.99 out
+ analog rail, +22.4 in, +19.4/+15.2 out
- analog rail, -22.6 in, -19.5/-15.4 out
measured ref to AGND TP102 + old TO220 legs spots
and now to replace next group of components
must be a strange sight, a crude "plugin" board :P
interesting part about this temp sub-board idea is that, the heatsink has magnets which further (try to) interface the heat out to the chasis (seperated by some kapton tape). so the capacitors are no longer "harassed" by the VREG :P. hopefully this will also further reduce internal operating temperature (shaky hand photo yuck, but you all get the idea). however it may also add instability. cos there is much more temp diff in the inside air now, but i dont know, lets see how it pans out.
-
continuation...
replaced 6x mmbf4393 (Q 104/105/113/108/109/120), 1x LTC2057, 1x OPA2140, 2x BC560
the E14 LTC2057 arrived with a dented pin (see pic) such a sensitive IC ... :'( ... i should replace it? o nvm, its just a bit of experiment :P
firing it up, the reading is somewhat crazy, there is still a residual float voltage which i dont understand its origin (inputs open). example : 1v range open, the jumping residual is also about 1v LOL ! how can this be? !!!
when inputs are shorted they behave like shorted, and there seems to be no components heating up especially because of this short :-//
anyone want to throw me some ideas where this residual float could be from?
but even with such a "flaw", the shorted noise @ 1NPLC 100mV even without top cover on, is impressive !
looking at the running numbers, it feels like i am running NPLC10-ish. i shall update plot when log is done :P
the FLIR shows the temp overview, with peak spot 41.7C on the OPA2140. the dark cluster (TO92) diagonally above it is the zero-buffer power regulation going to LTC2057. and further diagonally is the AD706
-
i am excited to say what looks like a interesting big leap in noise reduction (or somewhat).
this is NPLC 1, 100mV, AZERO=on, no REL/AVE. top cover is open (with slight draft)
sampling 2Hz, 3600samples/30min
on checking previous logs. the "width" p-p drifting about seems to be as low as old NPLC 10 log (if not, possibly lower than 1uV). this is quite fascinating. the 2 stars of this experiment 1) http://www.ti.com/product/opa2140 (http://www.ti.com/product/opa2140) 2) http://www.linear.com/product/LTC2057 (http://www.linear.com/product/LTC2057)
(and possibly helped from an extra stage of linear regulation? maybe?)
due to suspicion of another fault lurking somewhere, i will fall over into spasm if later i find that the unit cannot measure any voltage at all :-DD but only measure shorted noise !
** edit .... i couldnt help but laugh at myself when the plot appears. best pre-xmas surprise present?
again 1NPLC conditions, but covers closed, log restarted same 3600samples/30min
this is just crazy, before this mod, 1NPLC noise is like bloody 3.5uV p-p
-
:-DD the result just blows myself away :-DD
1 NPLC 100mV AZERO=on, no REL/AVE. ambient 27.8C, DMM internal 40.4C, hum 67%
3600samples @ 2Hz (30min)
AVE : -2799.82nV
skew: 0.1187
kurt : 0.0209
STDEV : 133.98nV (SHIT !!! thats really low) (145nV)
p-p : 893nV (986nV)
EDIT : compared to my previous NPLC 10, this bloody NPLC is LOWER in noise than my OLD log (in blue) ! SHIT !
edit ** mini blower fans have arrived 12v 70mA. to aid in internal air circulation. the current repaired logs are w/o fan.
internal fan added plot test, and it appears there is yet another component having ability to send out tiny spikes (plot 2306). with this plot,
STDEV : 135.42nV, p-p : 938nV. internal temp 41.3C.
with the p-p narrowed, the tiny air current seem to be able to make fluctuations in the plot
-
according to the service manual, when 1000v/100v range is engaged, the solid state protection segment is "OFF". what i dont understand is i do not see a active power turning on/off the 2 MOSFET. can someone enlighten me how does using 3 opto-isolator switches those 2 devices on or off?
after seeing this http://www.discovercircuits.com/H-Corner/bidirectional%20solid%20state%20relay.htm, (http://www.discovercircuits.com/H-Corner/bidirectional%20solid%20state%20relay.htm,) i am starting to understand, but the optos get induced voltage?
in the previous short circuit fault, where U114 was fried, it may have caused some inconvenience to U107, if U107 is damaged, will it cause -ve voltage to creep into "HI" input rail? the previous fault observation was that likely U114 pin5 became shorted to -15, this caused VR105 to go hot (in actual circuit VR105 polarity is reversed)
i think the extra fault is lurking somewhere here, where some -ve voltage leaks into "HI" input rail
*edit plot insert (all are 1NPLC AZERO=on, no REL/math/AVE)
@1kV, STDEV = 110.41uV, p-p = 688uV (plot 0005)
@100v, STDEV = 36.6uV, p-p = 254uV (plot 0050)
@10v, STDEV = 1.093uV, p-p = 6.3uV
yep there is def something else i need to shoot, as the range shifts from 100/1000v to 10/1/0.1v. the average swings from +ve to -ve :P. more JFET perhaps :P
idea for next mod, maybe i should just really stick the TO220 VREGs to the metal chasis via some solid insulated heat spreader ! MICA film ?!?
-
Open circuit readings are mainly due to bias and leakage currents. So after lots of soldering leakage currents can add up. Also changing the FETs and OPs can increase the bias. Keithly used the rather high noise LTC1050 because of the low bias - though stragely for bootstrapping they used the AD822 that may have quite some bias.
You can measure the current by having a large resistor (e.g. 1 M) acoss the inputs. Usually this should be less than 20 - 100 pA (depends on DMM model).
The LTC2057 is much lower noise than the LTC1050, so no supprise to see less noise. Now the following stage and the adc itself might be higher noise. The down side is the possible high bias current and thus some offset.
2 of the 3 Optocouplers at the input protection are not normal ones, but photovoltaic types: they have large Photdioes (several in series) at the reciever side and worke like a weak, low noise isolated floating power supply. The two mosfets are there to short out the protection resistors when the volateg signal is inside the valid range. This is done to reduce noise.
If turning off the FETs does not work some parts may get fried in case of high overvoltage (e.g more than 100 V) at the input. So before testing with higher voltage you should check this part: at least looking one the sending side of the optocoupler and measure the voltage of the floating supply. Also check the FETs for conduction (might got damaged by ESD).
-
mmm i have to dig deeper, maybe desolder and check each opto unit :-//
with my UNI-T jammed into the input jack, the handheld register about 140mV voltage in the low range (feel like too high to me), and something else in the 100v/1kV range cant rem what it was. the JFET in the switching array is all swapped except for ohm source, i cant find the J270, i am suspecting this JFET as well, but im not sure. on the PCB there are about 4 kinds of switching JFET, but in schematic is only 1 type. i wonder, did previous owner repair it? haha !
on the tip of A/D side noise, there is a A/D gain stage using AD711, it sports an active offset nulling, would it be risky to replace it with a autozero opamp? i am thinking AD
if the optos are fried, im in deep shit as E14/RS here do not have those variant. except mouser/digikey. i hope i do not have to buy from them :(. the shipping is killer :'(. there is no indication in svc manual what voltage to expect from opto, so i think i just have to "grope" further to see how the opto turn it on. (btw do you know what could be a possible equivalent?)
for all the work and experiment, here is the summary of todays short tests (vs tests of old 10NPLC). 1NPLC nearly matches every 10NPLC done before. best part is yet to come, 10NPLC numbers and i think i will try NPLC 100 with more confident as the low noise now is really low noise !
(note that tests 1000/100/10 are using results of DMM standing upright on sides, 1v/0.1 are sitting flat. the side posture seem to be better)
-
The AD Gain stage is a rather tricky combination of 2 OPs. The lowe frequency part should mainly depend on the OP177, not the AD711. The noise from the OPA177 might still be lower that the LTC2050, at least at not so low frequenies. So I don't see a lot of room for large improvements there.
The whole setup is not made for very low noise - a really low noise unit would use the initial amplifier for at least some gain as well. But this would essentially mean a complete new design.
The next step would be checking for the input protection to work and check the bias current. I don't think more noise data are needed now. This bigger Problem is likely Bias current. 140 mV at presumably 10 M input resistance of the UNI-T meter would be something like 14 nA of leakage - this is way ( at least a 100 times) to much. Looks like a broken JFET or lots of flux / dirt. The better test would be just a 10 M resistor at the input.
The switching JFETs might have to be selected / tested low leakage ones. Also make sure to have the case closed, as thin SMD parts may react to light. No low leakage in bright light.
I won't exect the optocouplers to be fried - like LEDs they usually last quite long. The dataseet of the OK should give a voltage value and also the FETs have a voltage they like to have to turn on. Even then to little voltage to turn the MOSFETs on, would result in more noise, but not in a failing protection. The protection might fail if the thrid OK is not working but this should be a nore normal one. Also it should be possible to test this circuit rather well in circuit, by just looking at the voltages ( e.g. gate voltages of the MOSFETs, when changing the input voltage ( e.g 1 V range and test at 0 and +-20 V at the input).
P.s. just looked at schemattics: the K2000 uses one special photovoltaic OK and two more normal darlington ones. However this part looks rather strange so the K2015 might be different there !.
-
ah the entire PCB is IPA-ed and ovened dried (lost count, by now maybe washed 10th round). so i know for sure PCB wise it is flux-free. ahhhh the smell of concentrated alcohol when the oven door opens, maybe it is 1 month worth of beer there :palm: *hic*
i think i try JFET hunting. but i have no more spare mmbf4393. the other 2 suspicious candidate are a lm339 n DG211.
on the side note, i did measure a few JFET with high resistance when 4393 are suppose to be "open-ish" 100ohm? that would be a sure fire way to say it is a problem JFET wouldnt it?
also i am considering to try MMBF4416A, it look like a close match, with higher voltage rating?
-
The 4416 seem to be only 30 V (gate source) rated, this may be to little. So I don't think they are a valid replacemant, as they are used up to 30 V and possibly silghtly more. So they should be really specified to 40 V at least. With the gate open the resistance is not well defined. To get a usefull reading, have it connected to source or drain. Than something like 100 Ohms is correct.
For the LM339s it should be possible to measure the voltages at there outputs, if they are OK. It's usually a go - no go part. I would not expect a partially working one.
I see no DG211 in the input part, that could cause extra leakage, and I won't expect to have one there.
One could do a few more measurements to check which of the FETs may be the bad ones. Interesting values would be the DC readings (0.1 V range and 100 V range) with 10 M between the inputs.
And the for an inital test one might get away with some, like the ones to turn on for ohms to be not populated.
It is also possible to have damaged a capacitor by excessive heat.
-
ok, now i see why even the mmbf4393 also spoil easily
https://www.fairchildsemi.com/datasheets/MM/MMBF4392.pdf (https://www.fairchildsemi.com/datasheets/MM/MMBF4392.pdf)
they are also 30v :(
i should say 4416A, they seem to be 35v
U103 = DG211, it switches front end stuff
100mV 10NPLC rough test, looks like a low p-p
**edit i went to search in mouser
how about BSR58 / mmbf4117. -40v
-
Mr popcorn noise is back. even being heavily messed about by pops and dips. this 100mV plot managed to hit STDEV of 58.95nV, p-p noise is just 430nV. the plot is 1NPLCx10REP, 2400 samples. the tolerance width is now so small, any small amount of pipsqueek noise will send the plot into a rollercoaster ! :-DD
update to show 3 plots, NPLC1x10REP, 0.7sec/sample, 3600samples
plot 1253, skew: -0.409, kurt:1.458, STDEV:72.46nV, p-p:611nV
plot 1153, skew: 0.016, kurt:0.084, STDEV:64.76nV, p-p:453nV
plot 1111, skew:-0.111.kurt:0-0.086, STDEV:66.97nV, p-p:436nV
all plots with fan, and now to try w/o fan.
looks like i will need to grab 1 of those $20 LCR to measure the JFET (n a short readup on JFET http://www.diystompboxes.com/smfforum/index.php?topic=100990.0 (http://www.diystompboxes.com/smfforum/index.php?topic=100990.0))
update plot, circular fan removed
plot 1429, skew: -0.011, kurt:-0.032, STDEV:51.24nV, p-p:375nV
it seems even the slow fan circulator has become more of a noise problem than it should
-
The MMBF4117 is rather high resistance. The 4119 would be slightly better (lower Ron). It schould be OK for some of the switches, but may not work well for all of them. E.g the two at the low end of the high voltage divider are better lower resistance type - possibly only one, for a more suitable part.
With these FETs you might have to check the specific manufacturer. For example the 2N4393 (TO18 Version) is rated 40 V in some cases.
U103 is in the AC part (behind the coupling capacitor) of the circuit - so no DC leakage from there. It seems to be for something like speed up of recovery from DC steps in AC mode.
If there was trouble with the input protection you might want to check the sending side of U107 (one of the optocouplers). This chip is also used from clampling - seems to be low leakage too.
There is really not sense in doing noise testing before the bias problem is fixed: you may have to change the LTC2057 worst case, this one possble source of the high bias. The other point to check is offset in the 100 V range.
-
i think NXP's is the next equiv http://www.nxp.com/documents/data_sheet/PMBFJ111_112_113.pdf (http://www.nxp.com/documents/data_sheet/PMBFJ111_112_113.pdf)
the 4119s to order is in 1000s reel, the NXPs to order is eta 2016 end of jan ???
i think this is all that is left with 40Vbr, https://www.fairchildsemi.com/datasheets/2N/2N5460.pdf (https://www.fairchildsemi.com/datasheets/2N/2N5460.pdf) --> 5462
ah P channel, wrong item ops
searching 1 tier lower, Vbr 35v, i get mmbf-J112/J111 from fairchild <--- i think i could either try this or wait for NXP
but best search result is the vishay, in the form of LM399 !!! :-DD
yea i know, logging anything in this state is pointless, but there is nothing else to do with the DMM atm. but i dont mind saving some "broken" data just to know it
i made some more measurement of the floating voltage
DCV 100mV, DMM = 3mV DC, uni-T = 140-150mV AC
DCV 1V, DMM = 4mV DC, uni-T = 135-145mV AC
DCV 10V, DMM = 4mV DC, uni-T = 135-145mV AC
DCV 100V, DMM = 2.5mV DC, uni-T = ~110mV AC
DCV 1000V, DMM = 2mV DC, uni-T = ~110mV AC
ACV 100mV, DMM = 23mV AC, uni-T = ~21mV AC
ACV 1V, DMM = 22mV AC, uni-T = ~20mV AC
ACV 10V, DMM = 27mV AC, uni-T = ~23mV AC
ACV 100V, DMM = 77mV AC, uni-T = ~21mV AC
ACV 1000V, DMM = 0.71V AC, uni-T = ~21mV AC
the pic is a screen grab off a low end dso, it is also the waveform i remember seeing going around the Q101/102. now that i recall these, i think it might be leakage from ohm source.
it seems net144/net140, which goes thru U107 to net145, could be the source of the leak, if gate leakages are the source.
-
The open measurements are pointless. To get a bias current reading, connect something like 10 M or 1 M between the inputs. Also the Uni-T meter might do it, if we know the input resistance. But this would mean using the DC mode. Also the polarity might be important.
Normally the voltage at U107 (sending side) should be close to zero ( < 5 mV), and U107 should not give significant leakage. I won't expect high leakage from this path unless U114 is broken.
One test to check the OPs for bootstrapping would be using the 10 V and 100V DC range, have something like 3 V at the input and measure a few voltages inside.
-
Very interesting thread. There is one thing I've noticed with K2000 vs K2015 and that is the K2015 appears to be more noisy (when shorting the inputs). I'm not the only one to have observed this, and my first conclusion is this is due to the DSP board along with its own mains transformer sitting right next to the input terminals. Of course this noise is still within specification, just not as good as the 2000.
I've also wondered if this is why Keithley unhelpfully disabled the BUILT-IN self check on the 2015, despite when looking at a hex dump of its firmware the code is all there!
One thing I did was swap the K2000 A06 firmware with my K2015 firmware just so I could run the built-in tests. This required a back up of the calibration EEPROMs of course. Interestingly the K2015 failed the first two tests 100.1, 100.2, but all subsequent tests passed.
I disconnected the THD board and ran the tests again and they passed completely! However, when I came back to it they kept failing again. I wonder if disconnecting the transformer would fix that? I was more concerned with all the other tests passing at the time anyway so didn't give it much further experimentation...
-
Noise at the gate of Q1 is not a problem. This MOSFET should be on when a normal measurement ( not 100 v or 1000 V) is done - the question is more the DC level, not the small noise.
The power for this part comes through the optocoupler from the 5 V supply - so noise is expected though filtered. It may be possible to do some more filtering here, but I doubt is will change much. I have not checked, but to get low noise the 5 V used here and for the input relays should not be the noisy digital supply. So a look at the 5 V (e.g. relais) might be a good idea.
More interesting testpoints would be pin 2 of U107 (optocoupler) or pin 7 of U114 (protecting ring at input) and pin 1 of U114 (protecting ring and supply of LTC1050). Also the output of the LTC1050 would be a good test point.
-
i think i solved it. it is the AGND. the ex AD822/OPA2140 cluster i thought did not need a AGND shortening before as it was only a guard/zero-buffer-floating, now due to the increased sensitivity, a AGND shorting to the rest of the clusters' AGND removed the noise !
(during the course i took a few more scope pics, including irrelevant noise of the 5000lm flourescent light, LED light, USB charge, etc. the equipment with the "pretty noise imprint is the nidec fan supply line. http://3roomlab.blogspot.sg/2015/12/looking-for-trouble.html (http://3roomlab.blogspot.sg/2015/12/looking-for-trouble.html))
now its quite clean !
(http://2.bp.blogspot.com/-AkZFkyTuc-M/VnH1buZiZ9I/AAAAAAAAChA/EzxdZJKBlRM/s320/20151217_070855.jpg)
on to log some more serious DMM noise !!! to verify the fix
edit : updated blog with caption notes
-
Lets see those results.
:clap:
-
NPLC10 warm up run, looking normal. no more squiggly dips n pops.
this skewed plot have a STDEV of 62.11nV, and p-p noise of 411nV
now that sensitivity is increased, maybe the entire AGND mod need to be expanded. maybe the opamp section need a tinfoil "hat". because waving my hands does change the guard output !
https://www.youtube.com/watch?v=m6GEJiMX5dI (https://www.youtube.com/watch?v=m6GEJiMX5dI)
-
The Tinfoil Hat goes without saying. But I think you have to get in touch with Monster cables for the interconnects at a minimum. But really I think they are cheap shit for low end fools. You should get some Nordost Odin, which is apparently 99.999999% oxygen free. :palm:
(Oh but a little more seriously, have you tried disconnecting the THD board and the transformer next to the input terminals? - surely Keithley know better, but why did they disable the BUILT-IN self test on the K2015? My own datapoint would suggest the extra THD board adds a bit of noise, but it's nothing more than conjecture at this point!)
-
The Tinfoil Hat goes without saying. But I think you have to get in touch with Monster cables for the interconnects at a minimum. But really I think they are cheap shit for low end fools. You should get some Nordost Odin, which is apparently 99.999999% oxygen free. :palm:
(Oh but a little more seriously, have you tried disconnecting the THD board and the transformer next to the input terminals? - surely Keithley know better, but why did they disable the BUILT-IN self test on the K2015? My own datapoint would suggest the extra THD board adds a bit of noise, but it's nothing more than conjecture at this point!)
im not sure if i have the budget to grab special materials like nordost odin, i am only reaching for what is convenient/feasible i atm. i have the idea to wire out a terminal block, instead of using the build in banana sockets, with that, it could be possible to chieve good results even without using premium copper :-//
yes i did disconnect the DSP this round to see if it does have a noise impact, but i will only know later with more logs. the pic attached is now what the current mod look like
*EDIT thanks to kleinstein for continually giving me tips for improvement n repair :P
-
Some shielding might help a little - though the main advantage would be likely in the very fast ( less than 1 PLC) modes, as a main funktion is to remove coupling to 50/100 Hz. Also HF coupling (e.g. from the DSP) may be reduced, but the influence of a shield that is not 100% closed on HF is hard to tell it tends to concentrate HF towards the edges, so a shield may make things worse at some places.
Whith changes in the AGND part, you have to be carefull, not to introduce errors or offsets. Usually Keithly do get the GND layout correct - adding extra connections may introduce loops and errors due to stray currents in some ranges. So even if the DCV ranges might get sightly better ohms or amps readings might suffer. So I would only add things after knowing exactly where in the circuit the extra connection is. For HF "noise" I would also measure first and solder only than.
There still seems to be quite some offset - keep that in mind too. Input bias currents or offsets are also important parameters for meter qualitiy.
-
@ macbeth, the moment you've been waiting for. guess which plot has DSP unplugged or which is the plot with DSP plugged/powered.
plot 0705 STDEV 142nV, p-p 1000nV
plot 1221 STDEV 145nV, p-p 1016nV
plot 1351 STDEV 145nV, p-p 977nV
-
i went ahead to do the "tin foil hat". i use some disposable aluminium kitchen baking tray to cut the "hats" n some kapton tape to insulate. 2 areas to experiment with, the GPIB digital section, the analog section with the sensitive opamps (top and bottom). to understand what noise is there
this is the example of the noise from VFD ribbon cable, just by pointing scope probe at it
http://1.bp.blogspot.com/-iei842h_OnY/VnHmQCkzEuI/AAAAAAAACgA/DLa8d7zdGL0/s1600/20151217_055434VFDribbon.jpg (http://1.bp.blogspot.com/-iei842h_OnY/VnHmQCkzEuI/AAAAAAAACgA/DLa8d7zdGL0/s1600/20151217_055434VFDribbon.jpg)
this is noise from U156
http://2.bp.blogspot.com/-vBNnQMlIjQU/VnHmTNGe8XI/AAAAAAAACgY/gHw3d2ZMfmQ/s1600/20151217_055558u156.jpg (http://2.bp.blogspot.com/-vBNnQMlIjQU/VnHmTNGe8XI/AAAAAAAACgY/gHw3d2ZMfmQ/s1600/20151217_055558u156.jpg)
scope parameter is 1mV/div, 1ms/div
i remember reading/seeing somewhere that sticking a metal foil on top of noisy IC help to absorb its EMI in the immediate "vicinity", i cant remember where to find this information anymore, i wonder if anyone know if this is true.
with the "hats" in place. here comes the logs.
the funny thing that happens now is that, there doesnt seem to be noticeable improvement, until i turn the unit on its side. so on top of being a EMI shield, it is also creating a separate thermal cavity which is helping the stability in some way. and due to the marked noise spikes, the p-p noise reaches 1152nV ! bah ! otherwise, the interesting setup gives a STDEV of 134nV (still way more noise than 1NPLC 54nV of keithley 7510 ! i wonder how much noise does 3458a has?). but by far, the improvement are also not by leaps and bounds without "hats". the majority of the noise is still the noisy circuits.
on second look, it doesnt seem like a very marked improvement, or maybe it needs a few more hours to settle ... ... ...
at a glance, it seem possible to lower even more noise (without the few spikes, the p-p noise seem to be around 750nV) if the tin hats can be painstakenly cut to "hug" the PCB on both sides, and set in place maybe with superglue? so in that way, 1 could then make a mini "great wall of china" around what needs to be "walled up". maybe? maybe not? :-//
>:D i need to destroy more noise !
-
The shield has mainly 4 effects:
1) line related capacitive coupling is reduces. This might be noticeable at less than 1 PLC readings, but likely not at 1 PLC and slower.
2) It will influence HF (e.g. 10 MHz range) "noise". However as the shield is not really closed in the HF sense, it is not clear if things get better of not. It temds to make things better, but not necessarily.
3) It changes the thermal design and keep turbulent air flow away from the circuit. This can reduce LF noise, as thermal EMF and local themperature variations are one nosie source in the sub µV arange. On the down side some part may get hotter as airflow from the fan may not reach the parts.
4) it makes capacitive coupling (especially in the ADC section) independent of external cable movements. But instead movements of the shield could have an influence.
Before more shielding is tested, don't forget the bias / leakage current. This is the first thing to be fixed. The changed OPs are a real improvement only if bias currents are stay small.
When lloking for noise reduction, it's a good idea to identify the soures, both from the theoretical side (schematics / caclulation) and measurements at different positions (e.g. compare noise in DCV and DCA modes and do the math). This really helps to find the weak spots and parts that can't be improved (e.g. resistors that need to be there). With the OP changed I don't know which is the main noise source now. Nobody cares about repeated noise measurement with just a shield more or less. The interesting part would be using the same setup and get data 0.1 V / 1 V / 10 V / 100 V and 10 A (or 1 A) range with the same NPLC setting (e.g. NPLC=10 ) - no need for really long datasets, just 200-500 readings without much drift are enough, especially if the same lenght is used for all sets.
The setup of the K2000 is not optimized for low noise (using AZ OP instead of low noise JFETs, separate buffer instead of amplification in first stage). So you can't expect really low noise like from the high end DMMs. Noise data for many DMMs are in the separate thread on DMM noise.
-
@ macbeth, the moment you've been waiting for. guess which plot has DSP unplugged or which is the plot with DSP plugged/powered.
plot 0705 STDEV 142nV, p-p 1000nV
plot 1221 STDEV 145nV, p-p 1016nV
plot 1351 STDEV 145nV, p-p 977nV
I would guess the middle one, because it showed a barely noticeable but worse change, so you connected it back for the last run ;)
So there goes my theory :palm:
-
the plot 0705 is reconnected DSP :P, the other 2 are w/o DSP on.
logging update:
after some hours of warm up. it does seem the "tin hat" did help squeeze down some noise. (these new plots are also with DSP connected). it also seem like 1v range more STDEV is experienced. the plots which represent "tin hat" are leftmost s/n 222-238 (bottom 1/3)
and strangely somewhere in between while i wasnt looking, the temperature dipped from 38.3 to 35.3 :-//
*edit
(pic 2, green = 10v 1NPLC overlay on red 1v 1NPLC, 10 units of red exactly sits on 1 unit of green "stepping") i did a small experiment regarding range/NPLC resolution which i previously did not understand. in 100mV range there is enough resolution to define 0.1uV, but as the voltage range scales up, resolution scales down equally. so i have to assume, every scaling up of 1 range, the NPLC (or REP) needs to be increased by x10, in order for minute changes in 0.1uV to be readable (100nV resolution which is in spec)
conclusion
100mV - 1NPLC usable to read 0.1uV
1V - 10NPLC must be applied to read 0.1uV
10V - 10NPLC*10REP must be applied to read 0.1uV
100V ? -1000NPLC?
1000V? - 10,000NPLC?
however it is likely this only applies to my modified K2015, as it now sits well below normal factory noise (or so i assume). it is likely a stock K2015 will need to apply NPLC10 to 100mV to resolve 0.1uV? maybe?
-
Comparing the noise in 100 mV (about 137 nV ) range and 1 V (180 nV) range, one can see that much of the noise is stil from the input part and ADC gain stage. Some noise is also from the ADC Stage, but not very much, even in the 1 V range.
The difference is due to reduced (by a factor of 10 in voltage and 100 in power) ADC noise in the 100 mV range. So in the 100 mV range noise from the ADC is still neglegible and even in the 1 V range it is still quite small: the about 180 nV in the 1 V range come from about 135 nV of the input amplifier and Gain stage plus about 80 nV from the ADC (inlcuding reference) itself.
Bandwith für 1 PLC should be 25 Hz plus an slightly uncertain part from the autozerophase. So getting date without Autozero might be useful. So the expected noise density is about 28 nV / Sqrt(hz) if 25 Hz bandwidth is assumed.
Known noise sources als the LTC2057 and the OPA177 (U132 in the gain stage) both at about 11 nV/sqrt(Hz) and something like 15 nv/sqtz(Hz) from R304 (20 K). Some more might come from the AD711 (U166) - I still don't see how exactly the two work together.
So much of the noise is acouted for, and not much is left to HF coupling or thermal effect (at least at 1 NPC). However thermal effects are often slower, so may show up stronger at 10 NPLC. So I don't see much more room for improvements without major changes.
Interestingly R304 is seem to be a large portion of the noise, but there is not much you can do about this as the resistor is needed for protection against overvoltages. In a carefull test one could get readings with this resistor shorted - but I would not change much there for later use. Data from the current ranges could give noise from just the gain stage.
-
this is interesting, the AZERO = OFF seem to permanently shave off a layer of noise. small, but it is removed. (last 3 log entry vs no. 242/243)
while in specifications AZERO is suppose to improve reading accuracy by 2ppm, it also seem to increase the internal p-p noise.
Before more shielding is tested, don't forget the bias / leakage current. This is the first thing to be fixed. The changed OPs are a real improvement only if bias currents are stay small.
i had a short check on this, it seem after the AGND shortening, the AC measuring of "signal" coming out of input socket is increased to about 650mV :palm:
i will grab some time to meddle in this area. it is likely due to a capacitor i added to the zero buffer, maybe :-//
a short check on ohms show that AGND shortening also turned back the zero reading more towards "zero", as initially, AGND shorting was only applied mostly to integrator side
moar experiments to follow ! thanks again kleinstein
(i wanted to use lower no of samples, but i think the higher samples capture alot of crap p-p noise, and it tell something inside is still noisy, when i started i used to see only STDEV, but that is averaged and does not tell instantaneous 1 of p-p problems, esp popcorn. then i added KURT/SKEW, so that it tells how "flat" is the noise, which STDEV also does not tell. i think DMM noise thread should use KURT/SKEW)
-
Wow your ambient temps are warm!
I'll repeat some of my tests with AZERO off, for comparison.
(Will have to be tomorrow night as the instrument is currently powered off)
-
Kinda doesn't surprise me to see a slight difference with AZERO off. To measure the zero offset you'd have to disconnect or float the input, measure, re-attach, math, for each read cycle right?
Wonder if Keithley has a paper on how that's accomplished?
-
This is sure a lot of posts about how to make a Top Tier manufacturer, current model, $4630 USD list price, meter "Better".
-
This is sure a lot of posts about how to make a Top Tier manufacturer, current model, $4630 USD list price, meter "Better".
Well this a well know watering hole for volt-nuts, is it not?
-
@ smokey , well i am still learning. thanks for everyones tips n nice technical threads that i can learn from. n of cos EEVblog for putting up with my immense nonsense :-DD and splatters of rather noisy pic / plots.
@ retrolefty, i cannot be classified as voltnut (and i have no qualification to be 1 anyway), the best VREF i have outside of a DMM is a voltagestandard from doug (not that it isnt good enough). i think voltnutters may need a diff certification standard to certify voltnut-ness, maybe to DIY a VREF of verifiable 1ppm nut-ness :-//. and to top it off, this K2015 is uncalibrated, i do not have the ability to define a volt accurately beyond 10mV (in my own opinion).
@ dr.diesel, i read in keithley pdf, azero on will make MCU measure VREF n zero when it is sampling input. i read that some suggests to improve sampling, instead of azero always on, they program it to cycle on/off once every minute. im not sure if newer keithley gear does it in per sample basis, the pdf seem to indicate the K2015/2000 does it on per reading/sample (i cant remember which pdf it was).
and to continue with some "fault" finding, i re-measured the floating "noise". (for ref, VR 115 and VR116 is swap around on my PCB, with pin 1 VR115 connected to source, not VR116 p2 to source). trace is for pin1 VR115 (which is tied to opamp input), vert is 250mV/div, horiz is 2ms.div (i beliv i made a mistake "zeroing" my scope previously and got the units all wrong lol). the huge signal is with uni-t plugged into inputs, however, w/o anything plugged in, the noise is very low pic-161054 (vert 50mv/div). shorting plug, noise is undecipherable on scope. i think the jagged noise has something to do with my neighbor's new air-conditioner installed today :(
my theory of this noise, is it could be the higher input impedance of new opamps. i derive this hint from trying to measure a 9v battery, after removing the input, the voltage take 10seconds to reach 1.5v, and is still trying to dissipate. hmmmm ... with the DMM powered off, pin 1 VR115 actually only have 116ohms to AGND (input low). i wonder, did the JFET have a switched sampling and forgot to on its discharge? or it doesnt work that way ?
next i try something, i tie a 1M R across U107 to AGND. this results in the next reduced trace pic-163734 (250mV/div).by doing this, it also destroys the DC accuracy :palm:.
next trace of +15 rail regulated noise, which i suspect the VREG did not fully regulate the input raw. causing the peak section to bypass more noise. :palm:
i think i should try to solve the DC rail first. maybe a PMOS/NMOS low drop stage instead of a LM29xx.
so... it seems i did not really solve the noise at all from that last AGND tie up *sigh*, i must have miss-read the noise with the input open.
as consolation to myself, i add this gif chart. some logs before i stop logging to do the above rummaging in the innards. note the log in bottom half with azero off, esp 1NPLCx50repeating-average. it seems it is quite capable of maintaining a very consistent /predictable error rate, which seems like a good thing in long term logging? yes? esp note logs which exhibit low KURT/SKEW = a flat-ish plot
-
This multimeter has a very high impedance imput, so for the 0.1 , 1 and 10 V ranges it is normal to have a rather poor defined response when open circuit. It is allready rather fast for the voltage going down from 9V to 1,5 V in only 10 s. In some sense this is good, as it indicates no excessive bias current but could also mean to low an input resistance. It is not unusual and nothing bad for an open input to slowly drifting all the way to its upper or lower limit. Watching this with a defined capacitor (e.g. 1 or 10 nF low leakage) at the input is one way to check for Bias currents.
The input resitance is specified to be very large (e.g. more than 10 GOhm), but usually is much higher (could be in the Tohms range). The other, usually more important parameter for the input is the bias current. Even if this should be in the 10s of pA range this does matter, as 10 pA flowing trough1 Mohm is allready 10 µV.
It looks like there is still some offset / bias errors to fix before looking for the noise. So far most of the noise is acouted for. So I won't expect significant improvements from shields or changes in the supply part. With now 3 noise sources of similar size that make up most of the noise, it is difficlult to get much better. Noise is allready something like 3 times lower than in the original configuration but this only helps if there is no excessive offset and bias currents.
There is also the possibility to have current noise at the input, so a test with something like 1 M resistor at the imput is importsant - there is absolutely for more of the same short circuit noise data.
-
ok so due to high impedance, the slow release of 9v measure is normal.
i jammed my uni-t at input in uA range AC, i could read an approx of about 0.07uA - 0.08uA. switching to 2W ohm, the uni-t itself have a impedance of 1kohm when measuring uA. and uni-t measures 101.06uA for the 2W mode (which i know is right on)
on capacitor mode, the uni-t sees the low range DC input as approx 330p. and hi range as approx 60p.
uni-t in AC mV mode, this time i can read the K2015 DC low range as 170mV, and high mode at 210mV approx. (looks like this property has changed). during 0.1v logging, the AC reading fluctuates to approx 165mV
in DC uA, there is nothing measureable by uni-t (K2015 in mV range)
edit : so i think it could just be be the VREG problem
edit ** i also took some time to retest some logs with the zero buffer. i removed 4 extra caps in the buffer section to see its effects. because i thought it affect the speed of decay in DC measure. without the need to post logs, generally its some increase in noise as usual, STDEV exceeds 140nV, and pp exceeds 1.1uV.
-
Without knowing the input impedance of the Uni-t meter, the voltage readings have no real meaning. Also the Uni-t meter will have there own bias / noise. So I won't use a second meter, except if you have a good pA - meter. The way to measure input bias is either a capacitor (and measure voltage over time) or a large resistor (e.g. 1 M or 10 M) and than use the Keitlhly meter to read. Both types of measurement measure slightly different things - so both ways may be needed to get a full picture.
In case the uni-t has 10 M input resistance, 170 mV of DC offset would mean something line 17 nA of bias -- this is about 1000 times to much.
-
not DC, that is AC 170mV
in DC uA, the uni-t could not read anything (0.00uA). input impedance in uni-t uA is 1k ohm
**edit well silly me, there is some oddity with the uni-t mV range. and now by accidently using V range. i could actually use the K2015 to measure itself. the K2015 measures the uni-t with approx 10.08M impedance, with that, the K2015 measures itself with a bias voltage of 0.6-0.7mV (approx 1NPLC) which = approx 65pA. did i derive this correctly ? (this is assuming uni-t have no bias to affect reading)
oh my goodness, that took me a long time to get at :P
-
The calculation is correct: 0.7 mV gives 70 pA of bias. This is not really bad, but also not as good as these meters used to be. I remeber a typical number of 30 pA for some HP meters.
This could be due the the extra current from the LTC2057 or changed JFETs. Also the Optocoupler U107 can contribute a little.
There a three types of bias:
1) leakage on the board, and chip cases - here guard rings and a clean board should keep this small, but some rest remains
2) semiconductor leakage (e.g. JFETs) - this part is temperature dependent, so keep the FETs cool
3) charge injektion from the AZ OP and the JFETs switiching for AZero.
The semiconductor leakage could be identified by changing the temperature of individual FETs. E.g. make the hotter or colder for soemthing like 10 K - this will about double or half that contribution.
Charge injektion from the JFETs should change with measurement speed, and essentially vanish if AZ is not used. So this is very easy to separate from the other parts.
Charge injektion from the LTC2057 should be a rather constant contribution. So there is a chance to compensate / trimm this to zero if needed. This would need a high value (e.g. > 100 M) resistor and a trimmer at the supply of the LTC2057.
-
i had another look at LTC2057, but there is no offset compensate pin. how do i accomplish this trim? (tried my luck at googling, but i dont think i understand what i should be looking for :P). (*edit 100M + trimmer from output to -ve?)
edit** i have added some python code which cycles AZERO every 100 readings or so. this will be interesting logs to see from here :P
-
There is no bias current trimming at OPs - at least I know of no OP that has this feature. However the special circuit used here with the other OP (now OPA2140 I guess) makes it possible to add a current. The supply für the LTC2057 is something like +-6 V relative to the input signal. It is relatively easy to use 2 resistors and a trimmer to get a voltage of something like +-10 mV relative to the output of the OPA2140. Then just have a high value resistor to make a small current in the +-100 pA range. The resistor will not decrease the input impedance by much, as its following the input on both sides.
However this would be only a last resort, to compensate the bias.
Its not just the LTC2057 that contributes (typical 30 pA). Also the OPA2140 will give a little current (likely not more than the original AD822) and the JFETs also can give some current, both as gate leakage and drain-source leakage for those that are off. Also the autozero step may add current by charge injection - this part depends on the NPLC setting: so measure the bias at 1 NPLC and a high NPLC and without autozero (should be independent on NPLC in this case).
The bias from the LTC2057 (and injection from the AZ phase) is special in that it is mainly temperature independent so it can be compensated. With the Gate leakage for the JFETs this is not that easy, as the leakage strongly depends on temperature. So compensation with the extra circuit should only be used for the fixed part.
The first thing would be identfying the sources, e.g. by cooling or heating the candidates for bias one at a time.
-
edit** i have added some python code which cycles AZERO every 100 readings or so. this will be interesting logs to see from here :P
In the simplest of comparisons, I ran a set back to back, one with auto zero on, one off and averaged the SD:
AZERO on = 0.397uV
AZERO off = 0.503uV
-
I have just finished repairing my two Keithley 2015 and opened a new thread about it (https://www.eevblog.com/forum/projects/keithley-2015-repair-and-the-input-buffer-replacement/).
Cheers
Alex
-
@ alex ... nice ! another LTC2057 mod !
@ dr.diesel ... it seems your AZERO is doing well. mine is a bit noisy
as an interesting note since playing around with AZERO. in the case of K2015, a AZERO cycle in a sample seem to add approx 20-60ms extra latency.
**edit, now that my K2015 have become a frankenstein. how do i characterize it properly? hmmm (but then again, there is still the uncertain input current + Q120/Q105)
(i might be using the word characterize wrongly)
-
To do a full caracterization of input current one would have to measure the input current at different input voltages.
There are two ways to do that:
1) with an external pA meter, peferrably battery powered
-> no need for high accuracy, just about 1 pA resolution over a +-200 pA range would be enough
2) having a good short time stable voltage source and a high resistor (e.g. 100 M or 1 G):
measure the volatage directly and with the series resistor. The differece comes from input current.
Well setteld batteries might be good enough as a low noise source (e.g. 0 , +-3 V , +-9 V)
For a < 200 pA spec, the 65 pA measured so far does not seem to be so bad. Maybe one has to live with that. Still have to check the current at about +-10 V - it is likely higher there. At least this should not be from the LTC2057 - it's current should be independent from the voltage.
-
im not sure if i understand correctly, but is this correct? (with the LMC662 representing the picoamp circuit described here https://www.eevblog.com/forum/projects/picoammeter-design/ (https://www.eevblog.com/forum/projects/picoammeter-design/))
:palm: polystyrene cap MOQ 10pc, each $2 ... o my !. i guess i cant have polystyrene
-
To do a full caracterization of input current one would have to measure the input current at different input voltages.
There are two ways to do that:
There is always a third way ;) . Log the voltage at 10V range, NPLC1, and discharge a charged to 10-11V polypropylene capacitor, say, 10nF, first time from +10V, second time from -10V. You need two runs as you don't know where/if the leakage current polarity changes. The speed of the voltage change is essentially the leakage current (i=C*dU/dt, for 10nF and 10pA = 1mV/s).
Cheers
Alex
-
In my Solartron 7065 manual it suggest putting the meter in he lowest range. Placing a 1meg resistor across the input and reading the resulting reading. It actually gives you picoamp input bias.
-
In my Solartron 7065 manual it suggest putting the meter in he lowest range. Placing a 1meg resistor across the input and reading the resulting reading. It actually gives you picoamp input bias.
Yes, however that would be the input current value only for one point in the range, close to 0V. The current changes (and in case of Keithley 2000/2015 - considerably so) over the input range from -10V to +10V. Discharging a capacitor would give a reasonably accurate result, taking into account the input capacitance of the meter (it is in my estimate is less than 1nF, which would give an acceptable 10% error for 10nF capacitor) .
Cheers
Alex
-
^^^ Thanks.
Im looking forward to selling that machine. I learned a ton about multimeters by poyring over its manual, and fixing it. Using tyat method to meazure the input current. Initially it gave 120-140pA. I cleaned it droppex to 60pA, resoldered the connections to the input relay 17pA. SUCCESS
then that rose to 40pA, i gave up.
-
To do a full caracterization of input current one would have to measure the input current at different input voltages.
There are two ways to do that:
There is always a third way ;) . Log the voltage at 10V range, NPLC1, and discharge a charged to 10-11V polypropylene capacitor, say, 10nF, first time from +10V, second time from -10V. You need two runs as you don't know where/if the leakage current polarity changes. The speed of the voltage change is essentially the leakage current (i=C*dU/dt, for 10nF and 10pA = 1mV/s).
Cheers
Alex
great idea, discharging 68nF in progress
i discharged from 7.4564v to 6.7629v in 20s. if using the equation, it gives 34.7mV/s. how do i compensate for charge voltage or the 68nF?
**edit round 2, charge @ 7.4558v, 200s, left charge @ 3.4587v, 20mV/s
round3 1.3671v discharged in 50s, 27mV/s
***edit re-experiment limiting to 20s each
start -7.2960v, end -6.6941v (68nF) 30.1mV/s -- 301pA/6.8 = 44.2pA ?
start +7.3356, end +6.7318v (68nF) 30.2mV/s -- 302pA/6.8 = 44.4pA ?
OTOH, if it is 300*6.8 = 2nA, that feels like the cap leakage i just measured instead
edit : if i use this tool http://www.learningaboutelectronics.com/Articles/Capacitor-discharge-calculator.php#answer. (http://www.learningaboutelectronics.com/Articles/Capacitor-discharge-calculator.php#answer.) and reverse estimate the resistor, it shows that the estimated current is really 2nA. o my
did i get this right?
**edit, after going thru the schematic. it seems it might have been the mmbf4393 gate leakage, the combination of so many of them? after going all ape over noise, now it seems i have to go monkey over leakage current? with that in mind i am beginning to understand why they have Q106/107, to balance out the leakage current, and why the advice to sort the JFETs
JFET gate drives
Q104 -15v DCV 11100
Q106 +15 balancer?
Q105 -15v 2w/4w 1111111/0000011
Q107 +15v balancer?
Q113 -15 2w/4w 0000000/1111100
Q108 -15v DCV 00011
Q136 -15v DCV 00011
Q114 -15v DCV 00011
Q109 -15v 2w/4w 0000011/0000011
Q120 -15v 1111100
**UPDATE... i couldnt think of a simpler way to repeat and vary this experiment, so i tried removing zener VR106, and wriggling the Fwd/R switch
and it seems it is the switch. again i use 20sec interval
start -7.2998v, end -7.1710v (68nF) 6.44mV/s -- *68 = 437pA (exceed 10G input impedance)
start +7.4257, end +7.2213v (68nF) 10.22mV/s -- *68 = 695pA (approx 10G input impedance)
DIRTY switch !
i dont think i am going to entertain myself changing the switch so i will clean it instead ! :P
-
Two of the JFETs are used as a diode for overvoltage protection and also compensating some of the leakage.
The calculation is about right, it's about 2 nA.
However the current is changing sign. So this is not bias current from gate leakage but more like an input resistance that is not high enough. So this might well be leakage due to dirt on the board or at the relays / switches.
2 nA at 7 V gives an input resistance of about 3.5 GOhm - so well outside the specs.
If in doubt with the capacitor, for a test you could check discharging disconected from the meter for something like 1000 s.
Hunting down leakage is a common problem in high impedance circuits. Not every isolator is perfect in the pA range.
-
The input impedance just in spec ( 10 G) is OK, one has to keep an eye on this - this may change overtime, with soldering somewhere or cleaning it again.
For characterization one could also have a look at noise current of the input. That is do noise test with a 1-10 M input resistor and without and compare. The LTC2057 has quite some current noise - this might be a problem if high impedance ( >1 M) signals are measured. In some AZ OPs the current noise can depend on the supply voltage - at least have a look at the datasheet.
Testing the Ohms ranges may be a goog idea if Fets have been changed. Though I don't expect big problems there.
If the fets at the divider were changes, the high voltage calibration (100 V range) might want a test.
A more comon mod might be adding isolation / shielding near the refference circuit. Here slow turbulent air flow can change temperature gradients and thus give small low frequency variations. This might reduce noise in the 10 V range a little.
-
completely bypassed input line from mechanical switch. input impedance +ve is slightly under spec @ 9G++, -ve is over spec, over 20G ?
it is as if a very small JFET leak favors +ve (too many JFET tied to -ve rail)
-
further "repair" of input impedance success
by swapping a 11v zener from VR115 to VR106 which i had suspected initially to have overheated from the short circuit accident. since VR115 did not need the pristine reverse leakage, it became the guinea pig for VR106. the input impedance is now over 10G ! hee hee, what a cheat, using the DMM own parts to service itself :P
plot input impedance vs 10v range input (68nF X2 cap)
thanks to alex nitin for this method 3 :P i would otherwise have no clue how to measure such low leakage
well this is weird, after ths above success, the input impedance returns back to 9G++
hmmmm ... do "senior" zener have such performance? esp when operating temp rises?
or it was sensitive to the IPA cleaning ... *confused*
**edit : due to the continuing frustration with the inconsistent 4mm banana socket, this is also BYPASSed with test leads now direct to PCB. and shaving off another small layer of noise.
-
Leakage in the 10s of GOhms range is sometimes tricky. One thing that can have an effect is humidity: above a certain level, that depends on the material , a surfcare layer of water is forming that can contribute to leakage currents. So to a limited degree (e.g. 10-20 K) it is positive if the circuit is warmer than ambient as this reduces relative humidity and thus formation of water layers.
It can take some time for IPA to fully leave some cracks or pores in the board material. So leakage can drift quite somewhat the first days after cleaning.
Chip internal leakage usually depends on temperature - so one can find leaky chips / FETs by heating them: if leakage get much hight with a 10-20 K temperature rise, the part is a critical candidate to look at. So leakage from inside the semiconductiors might actually be the easier part to locate.
As far as I see there are no zener diodes in the circuit that should contribute to leakage.: VR105/VR106 are bootstraped at the guard ring, not directly at the output. Only if leakage is very large ( > µAs range) this might give some contribution. One could check the voltage at the guard but I doubt this is the problem. This critical part in the overvolatage protection section is the optocoupler hold at low voltage (e.g. offset of OP). AS shown in the plan I have, VR115 is just bypassing a resistor - does not make much sense to me, so there might be an error in this part.
-
well swapping the zener produced some weird impedance results, now even after warm up.
i think ima have to change them all
it is as if, the fwd/reversed zeners have to be matched in leakage when in the same net
**edit
-
Without lables these graphs make no sense . What are they showing ?
The diodes should not be so critical as they are driven by the OP, not by the input signal. Only of they change the voltage of the guard this could lead to big trouble. The voltage at R122 would be an good indication - it should be small under normal conditions.
With the circuit around VR115 you have to check if the schematics is correct - I have some doubt there.
The diodes might be slightly sensitive to light, so keep the cover closed or at least avoid intense light.
-
ops sorry. that plot is Gohm vs voltage of 68nF discharging into input impedance
VR115 circuit is correct, VR106/5 is reverse
(i updated some schematic in K2000 repair thread here using kicad, https://www.eevblog.com/forum/repair/repaired-keithley-2000/msg814435/#msg814435 (https://www.eevblog.com/forum/repair/repaired-keithley-2000/msg814435/#msg814435))
after playing around, i think the graph is responding to p-p value self noise of DMM? if i change the sample width to measure the volt-drop/sec of the capacitor, the plot also changes the wave shape
did i make mistake? :-//
-
I think it is time that Dave make this ahole's information public. He seems intent on being as public an asshole as he can. So let's all know who to send the emails to.
-
The stange zagged curves could be just an artefact on how input resistance is determined. Could be something about rounding / digits.
With the input resistance is might be more usefull to look at it as input current versus voltage. By definition there should be only one input resitance as the sloop of input current versus voltage. It might be normal to get silghtly higher input currents as the voltage approches the 10/12 V nominal input limits. Finally the zener diodes set in slightly soft - thats normal and hard to avoid without bigger changes. The influence from the zeners will first show up as current to the guard OP - so you can check that.
As for the cause of the rather high input currents, I still suspect dirt on the board and maybe some of the changed FETs. Also the OPA2140 might be a candidate as it runs relatively hot - this change may not have been the best choice.
-
Hence I hold 3roomlab for all his tin-cap nuttery. I mean look at that poor 2000...it's just as insane as it gets.
My version follows, copper-hat for 3458A's A9 to test air current issue (~1ppm jumps)
(https://xdevs.com/doc/HP_Agilent_Keysight/3458A/img/copperhat_1.jpg) (https://xdevs.com/doc/HP_Agilent_Keysight/3458A/img/copperhat.jpg)
Proven useless, still doing jumps. ESD film under module is to make sure copper bottom film not touching A1 PCB.
-
I think it is time that Dave make this ahole's information public. He seems intent on being as public an asshole as he can. So let's all know who to send the emails to.
Oh no!! @3roomlab, I am 100% certain this message is not referring to your good self, but a miscreant known as mojo-chan. The deleted post leaves this one without context. :palm:
(BTW, it appears that the mojo self-doxxed in all his posts so no need for Dave to do that. I'm ashamed for my country he apparently lives in Portsmouth, UK)
-
@ macbeth, thats why now i like to delete my own old posts. but i do leave some relevant ones.
@ TiN, i think 3458a are so well designed, i doubt they have noise problems like keithley. well at least you have real copper hats :popcorn:. and i bet 3458a dont have AGND lines that measure 0.3ohm per inch :P. OTOH, if you keep autocal-ing, doesnt the 3458a work normally? but as it is, i think it does more good for impeding air currents.
today i tried some more tinkering. and i found something interesting. my version of PCB have these things missing (gif 1). i wonder what is the purpose of the JFET sitting in between?
i then scoped that line. ref C254 pin3 U132, vs U166 pin6. 10v range input is open, and input is shorted. amongst the signal, is also what seem to be a bunch of self noise as the opamp self amplifies
there is also the observation of pin6s of U132/166. when i try to read a battery. the yellow signal is suppose to be to A/D? but the noise, and there i spotted like somehow, the autozero interfering with the A/D signal, tiny spikes. this noise coincides with the way the NPLC/AZERO cycles the MUX (see the jpg of Q104)
and i also spotted a somewhat 1 inch trace AGND, and that somehow is 0.32ohms. making some noise to sit onit. this AGND is a new discovery running amongst the A/D MUX, which needs to ref right back to VREF, and here yet another AGND flapping around at around 0.25ohm between MUX and VREF. using analog scope, at 1mV/div, the probing this net turns a solid trace into a fluff, but the actual p-p cannot be seen properly (lousy scope i have)
i am tempted to add some kind of bypass, but it will just wreck the MUX signal for A/D. anybody have anyideas what to do with such kind of signal line? if magically, ferrite beads could appear in the copper line, would that be a possible solution?
the blue trace U132, is suppose to compensate AD711, but at the same time it injects the compensation signal as noise :(
sometimes i think, why is it so hard for them to put proper AGND plane? it is so weird they did the planes for the 2 digital sections. but did nil for analog. but in any case, im glad i got this unit for cheap :P
edit**
A/D MUX shortening of AGND return path, test plot. warm up 1.5hrs, 100mV/1NPLC/AZERO=on
plot 1446
3600samples STDEV 125.92nV, p-p 918nV
500samples STDEV 119.25nV, p-p 659nV <--- quite a large drop in p-p noise
plot 1516
3600samples STDEV 122.91nV, p-p 822nV
500samples STDEV 123.25nV, p-p 755V
looks like STDEV is under 130 for good? and p-p noise is under 1uV for good? :P
-
Copper pours on analog PCBs often could cause more harm than good, by adding capacitive coupling between sensitive signals. So more copper is not always a good thing.
-
More GND is not allways good. Also the resistance of the lines is not that critical, if the GND is used as a star ground -then it is important not to have some extra connections even if both a labeld AGND.
Especially those lines withou a solder mask are usally used as a guard to reduce leakage - there is only minute currents flowing there.
Measuring very small signals with the scope is often tricky where you have the GND connected - so the low level signal you find on AGND traces may not be real.
The stage looking JFET in the first picture is a kind of current limiting. It may have turned out that it is not needed - pissibly due to slightly different shitches (U163 and 129)
-
Also the resistance of the lines is not that critical
true, it only affected few tenths of uV/PPM. i am going to try more thorough cleaning, i hope i dont strip off the PCB traces and parts :-DD. i think i really need the input impedance back up over 10G, and prevent the NPLC/AZERO signal noise to exit into INPUT ...
**edit
as AGND is shortened more, the log results tend to appear more repeatable/predictable, instead of being plagued by random peak spikes (but i guess that is my only way of seeing it with my limited experience)
eg : now even disable AZERO, it also falls under 130nV and under 1uV pp noise (with similar looking result as AZERO on)
plot 1835, 100mV 1NPLC AZERO=off
3600samples STDEV 127.49nV, p-p 891nV
500samples STDEV 125.97nV, p-p 654nV
-
looks like i got it right this time. bought a really fine painting brush to "dig" under the SOIC/SOT23 with IPA (M-ohms vs volts plot)
again, the NPLC control signal seem to leak into the measurement side. and strangely, lower voltage seeming to give lower impedance.
-
It may take a few days for the last traces of IPA to be evaporated. It also takes a little for the system to warm up all the way - this can also effect the input currents. Warming reduces surface leakage but increases semiconductor leakage.
From the circuit there should be no difference between the 10 V / 1 V and 100 mV ranges - for the K2000 amplification is only changes in a separate stage after the input buffer. It could be just the sequence.
-
after abt 5 hours of warm up and rounds switching around capacitors, the impedance did increase ... by alot.
but at least, now the impedance vs volts are of the expected lower volts = higher impedance curve.
edit **
@34nF 15v 10s drop = 5.33mV/s, = 181pA, = 61.1G @ 11.1v
reverse @ 204nF 18v 10s drop = -1.39mV/s, = -284pA, = 39G @ -11.1v
the reverse character is slightly weird that it required alot more charge (4 to 6x) to make it past -11v.
is this what originally K2015 is in terms of impedance?
if so, it would mean that either i need to dampen the hyper sensitivity, or enhance it further with more attention to lowering of creepages?
(plots are Mohm vs Volts)
edit*** more testing
im not sure if im doing this right, but i have no other reason (or lack of reason) to think there could be something wrong
@68nF 10s drop -1.364mV/s, = -92pA, = 50G @ -4.70v
@68nF 10s drop 0.874mV/s, = 59.4pA, = 82G @ +4.93v
@68nF 10s drop -0.616mV/s, = -41.9pA, = 45G @ -1.88v <---- weird
@68nF 10s drop 0.306mV/s, = 20.8pA, = 92G @ +1.92v
geeez 82G impedance
-
This is what I get on my old and self-repaired K2000 by measuring the voltage drop over a 10MOhm resistor.
+10V: 63pA -> ~160GOhm
-10V: 15pA -> ~670GOhm
0V: -25pA bias current
To do the measurement a (short time) stable voltage source is needed. Connect the voltage source in series with the resistor to the meter. The resistor should the as near as possible at the HI input. Short the resistor. Read the voltage on the meter. Remove the short and read the voltage again. The difference is the voltage drop over the resistor.
-
im not sure if im doing this right, but i have no other reason (or lack of reason) to think there could be something wrong
@68nF 10s drop -1.364mV/s, = -92pA, = 50G @ -4.70v
@68nF 10s drop 0.874mV/s, = 59.4pA, = 82G @ +4.93v
@68nF 10s drop -0.616mV/s, = -41.9pA, = 45G @ -1.88v <---- weird
@68nF 10s drop 0.306mV/s, = 20.8pA, = 92G @ +1.92v
What type of capacitor are you using?
Cheers
Alex
-
@Alex, i am using this http://sg.element14.com/epcos/b32922c3683m189/film-capacitor-0-068uf-305v-20/dp/2334253 (http://sg.element14.com/epcos/b32922c3683m189/film-capacitor-0-068uf-305v-20/dp/2334253)
although i did not specifically note the voltage, 1 of it left from yesterday still carried about 7v of the test voltage of roughly 7.5v
some notes on noise after "restoring" the high impedance. it seems to be more sensitive to it self noise, more notably sharp spikes and a AZERO beat frequency (abt 350-400sec per cycle) which is now measurable by itself. plot 1206 azero off (STDEV 138nV, pp 959nV), plot 1052 azero on (STDEV 152nV, pp 1319nV, note sawtooth pattern). plots are nV vs seconds. in both plot the 3 "tin hats" are in place, temperature under the "hat" is @ 42.2C. 2 other plots also show similar beat freq and high spikes like plot 1052 with azero on, so it wasnt a coincidence.
since i couldnt see any other option to single out this spikey noise, i thought i just try re-running w/o the main "tin hat". and that, surprisingly reduced the noise. which i suspect might be just a temperature induced problem, w/o the tin hat, the analog section is now floating with the rest of the DMM temperature @ 40.2C. i am not sure if the tin hat have any electric field that could influence the guard, itself is tied to AGND, or maybe there should be a separate guard voltage for "faraday cage"? plot 948 azero off, (STDEV 127nV, pp 880nV), there are also 2 other plots with similar low noise, so this is not a coincidental capture either. it seemed like the same problem as the BJT popcorn noise encountered before, higher temperature = more noise.
with the hat off, i then also tried with AZERO on. this gives the plot 1139 (STDEV 124nV, pp 908nV exclude first 100 startup samples). it is purposely sampled at an odd 3Hz to see if it will pick up any beat frequency, but it appears maybe the AGND + tin-hat is the problem creating more noise,as there is no beat frequency visible and there is less serious wavy drifting.
**edit, the next plot is also a stable similar plot, looks like i can use AZERO perma-ON again :P as it has somewhat no percievable added noise
-
This is what I get on my old and self-repaired K2000 by measuring the voltage drop over a 10MOhm resistor.
+10V: 63pA -> ~160GOhm
-10V: 15pA -> ~670GOhm
0V: -25pA bias current
To do the measurement a (short time) stable voltage source is needed. Connect the voltage source in series with the resistor to the meter. The resistor should the as near as possible at the HI input. Short the resistor. Read the voltage on the meter. Remove the short and read the voltage again. The difference is the voltage drop over the resistor.
wow ! such high impedance !
i shall try it when i have parts. thanks for the info
*edit. what was broken in your DMM?
-
One should not convert individual inut current deadings to input impedance. The input current is from two sources: an bias current plus the current from the input impedance. So the -63pA / +15 pA at +-10 V is more like the -25 pA bias plus a 250 GOhms input resistance. Still good and about the right order of magnitude.
Higher temperature usually gives more noise, but this usually is not that much - usually something proprotional to temperature in Kelvin or the square root of it. One exception would be the leakage from semiconductors and the current noise connected to this. With a shorted input however current noise should not be important.
To check the effect of the AZ phase it might be interesting to check a non zero input signal. A simple battery at constant temperature (well insulated) gives a very low noise source. With a non zero voltage, the AZ phase might introduce extra noise / errors and it can be more sensetive to extra capacitance.
-
wait a minute, 250Gohm? is that the expected of bench DMM? that would mean my impedance is still too low?
hmm i dont understand what is azero phase?
**edit
i think i will add this info for other keithley users who are interested in the use of repeating average to extend NPLC. for comparison, the left plot is 1NPLC x 25 REPeating average (math wise it is 25NPLC), the right plot is NPLC5 x 5 REPeating average (math wise it is also 25NPLC). however @ 10v range, resolution down at uV level is very poor, so by averaging further a low resolution 1NPLC with higher pp noise, it will result in a weird "coarse" output, but an averaging of a finer 5NPLC resulted in a "finer" plot which resembles a more normal noise plot. maybe someone with more mathfu can give a more proper explaination, but in any case, this is again to show repeating average is usable as NPLC extension
**update
comparison of NPLC 10x10REP on left (~NPLC100) [STDEV 349nV, pp 2542] vs NPLC5 x 20REP on right (also ~NPLC100) [STDEV 316nV, pp 2325] . in this comparison, it seems the "finer" noise plot is on the right. NPLC2 x 50REP will also be done for comparison
edit** sanity check of NPLC x REP. i overlay a NPLC10 10v plot on a NPLC2 x 5REP 10v plot (~NPLC10). and the resolution lined up on the dot.
-
The specs of the meter are only > 10 GOhm. But much of the resistance is typical due to surface contaminations and similar leakage. So i can vary a lot from instrument to instrument. So the garantied miniumum is 10 GOhms, but the typical instrument will be much better, like in the 100-1000 GOhms range. However it might just take a bit of humidity or a little dust to change these values.
The Auto zero (AZ) works by switchung the MUX from the signal to GND for a short time. Here having a signal near GND is the easy case for the AZ. With a signal significant different from 0 it gets a little harder, as delays and possibly lossy caps can add errors. So to really test the AZ mode, one should do a test at higher voltage (e.g. 9 V battery).
-
progressing to rebuild another DC regulator to replace the temporary unit now inside, i need to find out if this is the correct way to put the zener for gate protection?
-
I would not change the supply regulation. There is not much (if anything at all) to gain from changing it, but much to loose - a not so well designed voltage regulator can easily turn into a power oscillator and damage quite a lot. So for the internal voltage regualtion the integrated regulators like 7815, LM317 are perfectly OK, they are quite reliable.
The still not so very high input impedance is more a question of keeping the board clean. Also repeated soldering could have changed to board material itself an added to leakage there - nothing you can do about it. Also the LTC2057 has a higher bias current, but this is essentially the price you have to pay for lower voltage noise.
-
back during post #71, i have already left the "building" with the 3 analog section VREGs all removed along with the main smoothing caps, heatsinks etc. they are no longer on the original PCB but on a sub-board above the GPIB section. (partially was i suspect, to have stressed them during a short circuit accident)
the main reason for the replacement is that, certain critical sections of the circuit (like the LTC2057) are powered by the unregulated part of the power.
happy new year everyone and happy modding!
-
The LTC2057 allready has it's own volateg regulation (the two zener diodes), and current sources give a rather good isolation from the rest. So any ripple / noise from that supply will not show up in the output.
With the updated OP (LTC2057 instead of LTC1050) there is not much more room for improvements: There is also no large unacouted noise source - so no chance to find a lucky magic cap that will give a significant improvement. For a significant lower noise in the low volagte (0.1 and 1 V) ranges one would need a radical different input amplifier design (no more separate buffer stage, JFET amplifier, AZ at front end) but this also requires different control (e.g. AZ mode) - so it's more like building an DMM from scratch.
It looks like the noise in the 10 V range is significat higher, when measured in volts. So the main noise source here seems to be ADC part of the circuit, not the input amplifier.
-
yea i think so too. while scoping the A/D MUX, i see the noise, but then again this is the only bench DMM i have taken apart, maybe this unit is way way out of spec since it is never calibrated from since 2007, maybe they forgot about this unit since maybe it could be badly out of spec / poor performance.
but so far it is all good, i am just tying up some loose ends (regulator/zener/JFET/optos), and i think it will be the end of DCV mods. then maybe i can start ... to calibrate, or start to make something to calibrate :P
-
Even with such an old DMM and with the modifications, there is not much you can do abput the calibration. It's verry likely still quite good. It's rather expensive to get a reference or meter good enough to make a true calibration - thats why such meters are usually send in to special calibration labs.
With the modifications it may not be mechanical stabe enough to do that. Also for normal private use, there is no real need for a fresh calibration. Even if 10 years old it's likely still good enough.
The only thing one can do is a plausibility check, to see if it is way out of specs.
-
i wonder, have anyone on this forum tried to self calibrate? and know what to expect? esp of a K2000, TiN?
it will be a waste to let such a "senior" LM399 lay idle, now that the front end is a diff animal from the original
**update
after reading some measurement articles again. i have come to understand uncertainty
= reading error + range error + tempco error
which means if a K2015 is to measure 10v on 10v range, 1 is to expect 250ppm/2.5mV uncertainty (for 90day, 20+5ppm). i cant find any 24hr accuracy numbers, so if i plug K2000 numbers in (15+4ppm), a 24hr uncertainty for K2015 could be 190ppm/1.9mV (all excluding tempco error which is 3ppm).
did i get that right? but now, how do you re-certify or certify a DMM still have such a range of uncertainty?
-
I've (part) self calibrated my 2015 DC which was consistently +30uV out to my other insruments and volt ref and my 2000 AC which was faulty when I bought it and repaired it.
Hint: Use SCPI for cal and you can go through the steps up to your abilities and then skip to the end and save. If you manually cal from the front panel then you have to go through the whole shebang, HV and resistance too.
I will emphasise I only "calibrated" my instruments to agree with each other and my cheap ass Hao Qi Xin volt ref. They are all singing from the same hymn sheet but are likely a couple hundred uV out from reality :-DD
Also, it is easy enough to make a backup of the calibration EEPROM using something like a TL866 and I highly advise you do this just in case! ;)
I'm looking at making a better volt ref (though my Hao Qi Xin is remarkably consistent at 10.00275V!) and also making a HV supply tracking a ref using a esi Dekavider I recently obtained, or else going the DAC route.
-
i see, looking at the service PDF. i think i have zero gear to try anything serious atm, unless only shorting.
it is good to know i could selectively 1) SCPI init cal 2) choose cal/steps 3) save/lock. that sounds simple enough.
the AD584 you mentioned, i think there is no more L version. i guess i might try to grab a K version, just for sanity checking.
i just managed to finished NPLC1000, 900 samples @ 0.1v. just to see its plot.
@ 200 samples, this NPLC1000 have STDEV of 26nV and pp of 163nV (which is = NPLC 10 of dr.diesels 7510, wow haha, old machine 100x effort to reach same STDEV)
**updated NPLC summary (10v +NPLC 500)
-
For an absolute voltage reference, one can buy a reference circuit that is calibrated. This is usually much better than the bare ref. chip. So it's something like a small board with a AD58x , max6350 or similar that someone with supposibly a good DMM has measured. So you the board and a note about the measured voltage.
-
further experiment
substituting JFETS Q109 113 120 with MMBFJ113 (40v NXP)
and changing new 11v zener DDZ11ASF-7
input impedance takes a dive, but it no longer shows the large "NPLC" timing artifacts
plot is V vs Gohm
tried a 2nd plot NPLC 2 for sanity check
and the 3rd NPLC 6
it is as if the J113 switches better?
**update after 2nd wash, the +ve impedance is still not "happy"
-
after making some inquiries to some china shops selling AD584 type references, i think this time of the year is a bad time to order anything serious. as new year just flipped and chinese new year will be here soon. it doesnt seem like serious gear can be produced seriously ever since from last month. :P ... time for long long long wait me thinks
Where are you located? (your country tag is broken for me =P)
If you're local I can measure something for you to about 8ppm uncertainty (95%) on 10VDC, otherwise, the shipping charges from Australia is more than enough to build up some nice LTZ1000 references. :P
I think there's a good chance your meter is still within 1 year spec. I have an old 34401A from ~1997 that has never been adjusted, and it reads 19ppm high which is basically the 24 hour spec. ^-^
-
thanks for the offer @deadly lover
i am inside a tiny "village" with 2 humongous gambling resorts :popcorn: ... singapore
i did think about LTZ1000, but atm to keep things simple, the cheap AD584 looks like a step i can take more easily. i dont think i will be sending anything "active" out to fellow forumners to ascertain any kind of standard. but i might take up your offer to measure some passive 0.01% resistors? (they are cheaper and lesser hassle to move around?), or maybe i would ask if the local tek centre can validate resistors :-DD, but i dont think they will, judging from the 14-16 days they need to reply a calibration email :palm: :-DD, they then re-routed me to a 3rd party lab instead of a proper follow up. :palm: i have no idea how things work in tektronix. so i might just try to calibrate this gear my self :P
-
The 4393 and J113 fets seem to be more or less identical - depending on the manufacturer. Sometimes the 2N4393 seems to be specified for lower leakage and would thus be better. Also the voltage rating depends - sometimes 30 V,35V or 40 V. Anyway the garantied specifications are something like < 100 pA, sometimes even only < 1 nA.
What you want in this application is more like <10 pA at 40 C - so not every unit will work, thoug h many will be likely acceptable. So one might want to check the fets before soldering them and than hope soldering does not change to much.
The three changes fets are more or less used in ohms mode only, so they Q113 and Q120 might contribute to leakage in DC mode - Q109 should be isolated anyway. The strange jagged curves are more like an artefact from rounding, calculation the slope, so nothing to do with the hardware.
-
thanks for the offer @deadly lover
i am inside a tiny "village" with 2 humongous gambling resorts :popcorn: ... singapore
Hmm actually, I sometimes find myself at Changi Airport for a short 3-hour layover once or twice a year, I remember seeing a postal service there that I could use right? I might be swinging by within the next 2-3 months.
-
100v VREF ... in theory for now (updated using AN19fc , fig 30 method)
i think i have got some parts of the PWM wrong :P
(gladly appreciate any tips on this 1)
the VREF side approx draws 10mA (in simulation, R6=1k, lower R6 = lower draw)
exploring possibility of
":CAL:PROT:DC:STEP5 100"
**update
i think i found some new problem again ... ohmmmmmmsss
plot of ohms vs seconds. PTF56 10k verified (voltage-std) ... but whats with the rainbows? :P
awaiting next batch of JFET 40v 4393/J202
and in the course of discovering keithley 2700 PDF, i discovered my ohms section is indeed faulty from a long time ago
https://www.eevblog.com/forum/projects/keithley-2015-repair-and-the-input-buffer-replacement/msg825815/#msg825815 (https://www.eevblog.com/forum/projects/keithley-2015-repair-and-the-input-buffer-replacement/msg825815/#msg825815)
-
For generating the raw 110 V, I would consider a royer converter. Its rather simple and low noise because its resonant - just no regulation but a fixed voltage ratio like a transformer. Winding the transformer is not that difficult.
The linear amplifier part look resonable, except for the way the supply for the OP is generated - I would stick to the more classical resistor/ zener and emitterfollower.
The 100 V regulation has no provision for capacitive loading - so a few additions may help. It would also be a good idea to limit the current to something like 1 mA - just for the safety.
-
as with this very "noisy" thread about my adventures, (after many weeks of toying around with my used K2015) i am walking around a large unknown building called "calibration and adjustment" of DMM trying to go inside and play. and while looking at some ebay stuff, i stumbled on something familar, this VREF unit called the D105 that claim to have 2ppm stability (some of you know it has a famous thread in this forum). and i came back to re-read some of the stuff in there. edit** i have parts i do not understand, hopefully somebody who knows more can enlghten
having experienced the kind of noise i dislike, i saw the last few posts where blackdog showed his quad REF based on linear VREF vs the D105 comparing stability and noise. and then on closer look i started to notice something about the D105 plot, which now on 2nd pass, i started to understand what all the accuracy and low noise could possibly mean.
i (hijacked 2 plots from that thread) superimposed 3 plots, blackdogs' quad VREF 10v, 1 of my best 10v NPLC100 (plot 15-Dec30-0101_LOG.ods) shorted test run and D105's 10v (in correct order as it appears in the pic, top middle and bottom). but as i didnt want to squeeze more of the K2015 plot into a smaller volt scale, i have to offset it and show it as double the original Y-axis size (the left side still showing the 2000nV Y-axis size). for explaination, i have sized both yellow plots to have similar Y scale size, which is the original 2uV per div, my shorted plot is magnified 1uV per div. the X scale is nearly the same for all 3 plots at 6min per div or 1 hour total.
if the VREF have very high noise, it will add this noise/uncertainty by its high rms noise value? or by its pk-pk ? is my understanding here correct?
so if i imagine (if i want to calibrate or adjust this DMM in this 10v scale) my DMM shorted STDEV uncertainty = 0.3uV, D105 STDEV noise = assume @ 2uV, the instance of measuring this D105 uncertainty = 2.3uV ? and if i use a better VREF source like blackdog's, if the uncertainty is assume @ 0.4uV, then this instance of measuring the uncertainty is 0.7uV ? do i sound right in theory?
-
from this article
https://www.wmo.int/pages/prog/gcos/documents/gruanmanuals/UK_NPL/mgpg11.pdf (https://www.wmo.int/pages/prog/gcos/documents/gruanmanuals/UK_NPL/mgpg11.pdf)
page 5
As a ‘rule of thumb’, roughly two thirds of all readings will fall between plus and minus (±) one
standard deviation of the average. Roughly 95% of all readings will fall within two standard
deviations. This ‘rule’ applies widely although it is by no means universal.
which means if i measure 10v, with my STDEV being 0.3uV, my reading uncertainty should not just be +/- 0.3uV but should be +/- 0.6uV ?
-
Noise from uncorrelated sources adds as power not as voltage. So if you have 2 µV and 1 µV from two noise soures, the resulting noise is not 3 µV but the square root of (2²+1²) µV or about 2.2 µV.
The uncertainty given as a +- value due to noise is usually 3 times the RMS value, though this can vary from context to context.
When doing a calibration / adjustment, there is usually enough time to use a long integration / averaging time. So noise is usually not a problem in this context. A problem might be high 1/f noise - here longer averaging does not really help.
-
i had a peek at what is going on in my local national met lab, they are using k=2. they are based on this french lab http://www.bipm.org/en/bipm-services/calibrations/cms_em.html. (http://www.bipm.org/en/bipm-services/calibrations/cms_em.html.) i assume that they are not the only entity doing this service to every country, they look like contractors which anybody with alot of money (and scientists / gear) could setup and run.
Here is the fixed link for you! (http://www.bipm.org/en/bipm-services/calibrations/cms_em.html)
(You left a full stop '.' at the end of the URL so it failed ;) )
Both links look very interesting :-+
-
i had a peek at what is going on in my local national met lab, they are using k=2. they are based on this french lab http://www.bipm.org/en/bipm-services/calibrations/cms_em.html. (http://www.bipm.org/en/bipm-services/calibrations/cms_em.html.) i assume that they are not the only entity doing this service to every country, they look like contractors which anybody with alot of money (and scientists / gear) could setup and run.
Here is the fixed link for you! (http://www.bipm.org/en/bipm-services/calibrations/cms_em.html)
(You left a full stop '.' at the end of the URL so it failed ;) )
Both links look very interesting :-+
ah thanks
ok 10 months of me in a time machine away from the bench ... i had to re-connect the last question (10months ago) which i didnt quite understand
in the multiplying of the STDEV/RMS by 3, is it related to what is called coverage k value in this document (https://www.wmo.int/pages/prog/gcos/documents/gruanmanuals/UK_NPL/mgpg11.pdf (https://www.wmo.int/pages/prog/gcos/documents/gruanmanuals/UK_NPL/mgpg11.pdf)) page 23 item 7-4. which then makes confidence level of the uncertainty to 99.7% ... i think.
i had a peek at what is going on in my local national met lab, they are using k=2. they are based on this french lab http://www.bipm.org/en/bipm-services/calibrations/cms_em.html (http://www.bipm.org/en/bipm-services/calibrations/cms_em.html) i assume that they are not the only entity doing this service to every country, they look like contractors which anybody with alot of money (and scientists / gear) could setup and run.
if i understand the 28nV/V correctly, am i right to say it is saying their 10v reference is 0.28ppm in uncertainty?
-
28nV/V is 0.028 ppm.
The web page is from the french metrology lab, it's the JJA they use and the limits of there comparison tools. So no surprise to find a really good value - but likely rather expensive. This is more like a lab where normal calibration labs may send there high end calibrators.