paralleled Buffer Outputs - Current Share Resistors necessary?

[Andree Henkel]

Hallo, I use a double Buffer 74LVC2G17 to boost current drive capability of a clock I generate with a LTC6905.
Question is, do I need resistors at the outputs of the single buffers, bevore combining them. And if so, what are reasonable values?
So far I skipped them and got no problems, but I´m not sure if this is a clean solution. My worry is, the delays and rise / fall times although same die and length matched layout may slightly differ so I basically get short time "bus contestion" situations at switching where one buffer sources current into the output of the other.

[tggzzz]

Hallo, I use a double Buffer 74LVC2G17 to boost current drive capability of a clock I generate with a LTC6905.
Question is, do I need resistors at the outputs of the single buffers, bevore combining them. And if so, what are reasonable values?
So far I skipped them and got no problems, but I´m not sure if this is a clean solution. My worry is, the delays and rise / fall times although same die and length matched layout may slightly differ so I basically get short time "bus contestion" situations at switching where one buffer sources current into the output of the other.

More of a problem: high ^di/_dt inducing voltages in Vcc/Gnd leads, and transmission lines/loads on the board.

[CaptDon]

Just make sure to have some good bypass capacitors on the supply rails right at the buffer package. We have done some very unacceptable things like stacking 74LS245 etc. on top of each other or paralleling all the inputs to a buffer as well as all of the outputs to directly drive 5VDC relay coils or even incandescent panel lamps. Sometimes you 'just have to do what you have to do' when a test fixture for a one off product needs to be built overnight! Anyway, you should be fine, the delay mis-match at most would be expected to be under 1 nanosecond. Anyone remember seeing as many as 4 2102 ram chips soldered on top of each other with the chip select pins bent out and hardwired? Those were the days, turning a 4K X8 into a 16K X8 or sometimes just an 8K X8. Fun times!!

[tggzzz]

Just make sure to have some good bypass capacitors on the supply rails right at the buffer package. We have done some very unacceptable things like stacking 74LS245 etc. on top of each other or paralleling all the inputs to a buffer as well as all of the outputs to directly drive 5VDC relay coils or even incandescent panel lamps. Sometimes you 'just have to do what you have to do' when a test fixture for a one off product needs to be built overnight! Anyway, you should be fine, the delay mis-match at most would be expected to be under 1 nanosecond. Anyone remember seeing as many as 4 2102 ram chips soldered on top of each other with the chip select pins bent out and hardwired? Those were the days, turning a 4K X8 into a 16K X8 or sometimes just an 8K X8. Fun times!!

Yup, I remember those.

Nowadays it is done in-chip; look at flash memory chips' cross section

But be careful with 74LVC1G devices. I have three of those with 143ohm series resistors driving 2.5V into a 50ohm transition line with a <300ps transition time.

[Andree Henkel]

Thank you all.
I´ll look to provide proper decoupling.
My layout will be very compact, so the round trip delay at buffer output to load will be lower than the rise/fall times.