VHDL help- Case statements, and declaring multi-bit signals!

[McPete]

Hey all,

Just putting together my first little FPGA configuration for my technical college class on VHDL- It's the first time they've taught it, so the instruction was "Go figure it out." I THINK I've got something that should work, but I'm getting a few compliation errors. If a few of our number who are experienced in the ways of VHDL could set me straight, I'd appreciate it!

What I'm trying to create here is a greycode-to-bcd decoder. I think the case statement is right, I'm just not sure about my signal decs... I'm using the Quartus II IDE, for reference. Here's the code;

Library IEEE;
USE IEEE.std_logic_1164.All;

Entity Decoder
inbit0; inbit1; inbit2; inbit3         : IN BIT
outbit0, outbit1, outbit2, outbit3      : OUT BIT
End Decoder

Architecture Decoder_behaviour of Decoder Is

SIGNAL greyin   : BIT_VECTOR(0 to 15)

SIGNAL bcdout   : BIT_VECTOR(0 to 15)

BEGIN
greyin <= inbit0 & inbit1 & inbit2 & inbit3
bcdout <= outbit0 & outbit1 & outbit2 & outbit 3
PROCESS(greyin & bcdout)

BEGIN
Case greyin IS
when "0101" =>      bcdout   <= "0000"   -- Zero
when "0100" =>      bcdout   <= "0001"   --   One
when "0000" =>      bcdout   <= "0010"   -- Two
when "0001" =>      bcdout   <= "0011"   -- Three
when "1001" =>      bcdout   <= "0100"   -- Four
when "1000" =>      bcdout   <= "0101"   --   Five
when "1100" =>      bcdout   <= "0110"   -- Six
when "1101" =>      bcdout   <= "0111"   --   Seven
when "1111" =>      bcdout   <= "1000"   --   Eight
when "1110" =>      bcdout   <= "1001"   -- Nine
when "1010" =>      bcdout   <= "1010"   -- Ten
when "1011" =>      bcdout   <= "1011"   -- Eleven
when "0011" =>      bcdout   <= "1100"   --Twelve
when "0010" =>      bcdout   <= "1101"   -- Thirteen
when "0110" =>      bcdout   <= "1110"    -- Fourteen
when "0111" =>      bcdout   <= "1111"   -- Fifteen
End CASE
END PROCESS
END decoder_behaviour

Thanks for your help!

[jahonen]

I think you are missing several semicolons, port declaration in entity, bit vector lengths (indexes describe the number of bits the vector holds, not the value it represents) etc. Instead of describing all of them individually, I attached fixed version below (checked it with ModelSim so it should compile ok). BTW, I think it would be more appropriate to use std_logic and std_logic_vector datatypes instead of bit and bit_vector. Also, usually vectors are indexed from high down to low, so that high index is in the left. You could also put greyin and bcdout vectors directly to the entity port instead of individual temporary signals. However, don't worry, it will usually take a quite long time to master the VHDL "perfectly".

Regards,
Janne

Library IEEE;
USE IEEE.std_logic_1164.All;

Entity Decoder is port
(
inbit0, inbit1, inbit2, inbit3 : IN BIT;
outbit0, outbit1, outbit2, outbit3      : OUT BIT
);
End Decoder;

Architecture Decoder_behaviour of Decoder Is

SIGNAL greyin   : BIT_VECTOR(0 to 3);

SIGNAL bcdout   : BIT_VECTOR(0 to 3);

BEGIN
greyin <= inbit0 & inbit1 & inbit2 & inbit3;
(outbit0, outbit1, outbit2, outbit3) <= bcdout;

PROCESS(greyin)

BEGIN
Case greyin IS
when "0101" =>      bcdout   <= "0000";   -- Zero
when "0100" =>      bcdout   <= "0001";   --   One
when "0000" =>      bcdout   <= "0010";   -- Two
when "0001" =>      bcdout   <= "0011";   -- Three
when "1001" =>      bcdout   <= "0100";   -- Four
when "1000" =>      bcdout   <= "0101";   --   Five
when "1100" =>      bcdout   <= "0110";   -- Six
when "1101" =>      bcdout   <= "0111";   --   Seven
when "1111" =>      bcdout   <= "1000";   --   Eight
when "1110" =>      bcdout   <= "1001";   -- Nine
when "1010" =>      bcdout   <= "1010";   -- Ten
when "1011" =>      bcdout   <= "1011";   -- Eleven
when "0011" =>      bcdout   <= "1100";   --Twelve
when "0010" =>      bcdout   <= "1101";   -- Thirteen
when "0110" =>      bcdout   <= "1110";    -- Fourteen
when "0111" =>      bcdout   <= "1111";   -- Fifteen
End CASE;
END PROCESS;
END decoder_behaviour;

[FPGAcrazy]

Hi,

The example as posted has some mistakes as already pointed out by jahonen. First of all, if you would like to assign a bit vector to the input and output signals, a vectors should be used of the type bit_vector instead of this single value bit. However, in modern VHDL coding bit and bit_vector are not used instead std_logic_vector, unsigned and signed are used for vectors and std_logic for single signals

The use of these constructs is illustrated in the following example

library ieee;
use ieee.std_logic_1164.all;

entity bcd_7seg is
   port (
      bcd : in std_logic_vector(3 downto 0);
      seg : out std_logic_vector(6 downto 0)
   );
end;

architecture rtl of bcd_7seg is
begin

   process(bcd)
   begin
      seg <= (others=>'1');
      case bcd is
         when "0000" => -- 0
            seg (5 downto 0) <= (others=> '0');
         when "0001" => -- 1
            seg(2 downto 1) <= (others=>'0');
         when "0010" => -- 2
            seg(1 downto 0)<=(others=>'0');
            seg(6) <='0';
            seg(4 downto 3)<=(others=>'0');
         when "0011" => --3
            seg(3 downto 0)<=(others=>'0');
            seg(6) <= '0';
         when "0100" => --4
            seg(2 downto 1) <= (others=>'0');
            seg(6 downto 5) <= (others=>'0');
         when "0101" => --5
            seg(0) <= '0';
            seg(3 downto 2) <= (others=>'0');
            seg(6 downto 5) <= (others=>'0');
         when "0110" => --6
            seg(6   downto 2) <= (others=>'0');
            seg(0) <= '0';
         when "0111"=> --7
            seg(2 downto 0) <= (others=>'0');
         when "1000" =>
            seg(6 downto 0) <= (others=>'0');
         when "1001" =>
            seg(3 downto 0) <= (others=>'0');
            seg(6 downto 5) <= (others=>'0');
         when "1010" => --A
            seg(2 downto 0) <= (others=>'0');
            seg(6 downto 4) <= (others=>'0');
         when "1011" => --B
            seg(6 downto 2) <= (others=>'0');
         when "1100" => --C
            seg(5 downto 3) <= (others=>'0');
            seg(0) <= '0';
         when "1101" => --D
            seg(4 downto 1) <= (others=>'0');
            seg(6) <= '0';
         when "1110" => --E
            seg(6 downto 3) <= (others=>'0');
            seg(0) <= '0';
         when "1111" => --F
            seg(6 downto 4) <= (others=>'0');
            seg(0) <= '0';
         when others => null;
      end case;
   end process;
end architecture;

This is fully working example which has been tested on a FPGA.

A free book is the VHDL-Cookbook http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf.
This is not a very good book but it contains the syntax rules and  should be used as a reference only.

Hope this helps

Johan

[patb]

A free book is the VHDL-Cookbook http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf.
This is not a very good book but it contains the syntax rules and  should be used as a reference only.

Thanks for the link to the ebook. Btw, would you recommend some really good book for complete beginner?

[FPGAcrazy]

Hi I have to admit that I learned VHDL many years ago. But I think I especially liked this book, although I am not totally sure(long time ago )

Digital System Design With VHDL, 2nd Edition
Mark Zwolinski
ISBN 0-13-039985-X

I had a quick look through the examples they use the bit and bit_vector in the begin but later on they use the std_ulogic_vector.

Some remarks. Be careful VHDL support many constructs of which only a small subset is suitable for synthesis.
You also need some simulation and synthesis tools which depends on your target device (silicon vs FPGA and so on). However, for most FPGA simple tools for small designs are free.

Have fun hacking.

[patb]

I've found this book also translated to Polish. It seems the author has some Polish origins (his last name is definitely Polish). Looks like it's something I was looking for. Thanks for the recommendation!

[McPete]

Hey all,

I've modified the file as suggested, but Quartus is still producing this error;


Error (10500): VHDL syntax error at project1.vhdl(29) near text "PROCESS";  expecting "<="

What am I missing here?

Thanks for your help all- This is one heck of a learning curve, especially when teaching yourself!

P.

[jahonen]

Hey all,

I've modified the file as suggested, but Quartus is still producing this error;


Error (10500): VHDL syntax error at project1.vhdl(29) near text "PROCESS";  expecting "<="

What am I missing here?

Thanks for your help all- This is one heck of a learning curve, especially when teaching yourself!

P.

I think it must be a typo or something like that, I tried the version I posted above and it compiled with flying colors, no problems at all with Quartus 9.0 SP2. Below is the synthesis result as viewed from Quartus RTL viewer. Looks ok'ish.

So I suggest to go through it once again.

Regards,
Janne

[McPete]

Ah, found it: I hadn't changed the "&"s to "," in defining the bcdout signal.

However, I'm now getting this;


"Error: Top-level design entity "Project1" is undefined"

What does that mean?

P.

[tinhead]

Ah, found it: I hadn't changed the "&"s to "," in defining the bcdout signal.

However, I'm now getting this;


"Error: Top-level design entity "Project1" is undefined"

What does that mean?

P.

go to Files tab in navigator, select the file which is defining the top level (e.g. decoder.vhd),
right click on that and chose "Set as top-level entity" ...

[McPete]

That was it! Awesome! Thankyou all, I'm on my way!