EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: miketan3904 on May 20, 2020, 12:32:43 pm
-
Hi guys! I have some questions regarding op-amp.
I know that the op-amp basically amplifies the difference between both of its input terminal, as shown by the equation below:
Vout = AvoVd
where
Avo = open loop gain
Vd =potential difference between inverting and non inverting terminal
When negative feedback is applied, the op amp will keep its input terminal at same potential if the open loop gain is infinite. The reason I know is as follow:
Vout = AvoVd
Vd = Vout/Avo
Therefore, if Avo is infinite, Vd will be zero. However, if Avo is finite, we would expect a small potential difference between the inverting and non-inverting terminal of the op-amp. All the reason I know is explained from maths perspective.
So, I would like to know the physical reason that causes Vd to be non-zero when Avo is finite (for example, does it caused by imperfection of transistors? If yes, what kind of imperfection is that?)
Thank you!
-
Only an ideal op amp (non-existent!) has infinite gain. Any real op amp will have finite (but normally very high gain).
In modelling it's convenient to assume infinite gain, as you are then able to use the "virtual ground" concept for the calculations.
If you want to have the precise closed loop gain, you need to use classic feedback theory.
This states that closed loop gain is equal to G(s) / [1+G(s)*H(s)]
Where G(s) is the forward transfer function (= op amp gain)
and H(s) is the feedback transfer function (= feedback network)
Setting G(s) to infinity, you can do a much simpler calculation.
-
OK. But then what is the reason that causes the op-amp open loop gain to be finite? (I know there is nothing that is infinity in this world though.)
-
Hi,
Is this a homework question?
Have you heard about input offset and bias currents?
Jay_Diddy_B
-
It is not of much use to think in terms as "infinite" for Opamp gain.
As a very simplistic model, it's useful as a first introduction for explaining opamps, but that is also where it should stop.
If opamps were close to those idealized concepts, there would not have been 10000 different versions of them (I guess there are more, but I never actually tried to count them).
The reasons there are so many different opamps is that there are many limitations in the physical world which cause differences between a real opamp and those very simplified models.
When I need to analyze an unknown circuit with an opamp. I approach it from a sligtly different view. When the input of the non inverting input is higher than from the inverting input, the output goes up (with a speed called "slew rate"). And when the other input is higher, the output goes down. Usually there is some feedback between the output and input which stabilizes the circuit. But even when there is not, this way of approaching an unknown opamp circuit lets you analyse it quickly.
Some of the most important practical opamp limitations:
* Bias current: Opamp inputs always must have a DC current path to work properly!
* Input offset voltage.
* Slew rate.
* Gain Bandwidth product.
There are many more limitations to practical opamps, but these are the most important.
-
So, I would like to know the physical reason that causes Vd to be non-zero when Avo is finite (for example, does it caused by imperfection of transistors? If yes, what kind of imperfection is that?)
On a monolithic integrated part, thermal feedback from the output stage to the input stage limits open loop gain below that of the cascaded gain stages. Thermal feedback also increases settling time beyond that predicted by the bandwidth.
Precision parts use a layout which provides symmetry between the input and output transistors to minimize effects from thermal feedback. But output loading should still be minimized and for the best performance, an external buffer used.
-
To swing the output from one voltage to another (for example, from +10 V to -10V in a dual-rail circuit) requires a change in the differential input voltage given by (dVin) = (dVout / K).
The actual differential input voltage Vin when the output is zero (or the middle of the range in a single-rail circuit) is called the DC offset voltage, and is typically a few mV.
The total range of differential input voltage is the change calculated above, centered on the offset voltage.
This is all in a linearized approximation, since the open-loop amplification is not perfectly linear, but it is close enough to answer your question.
For the 20V swing above, if the DC gain K is 200 V/mV (typical spec for TL071 for +/- 10V output swing), then the change in differential input voltage (for DC) is only 0.1 mV, but the range will be centered on the input offset value (+/- 3mV typical) and is much smaller than the typical offset.
The gain falls off with frequency, reaching unity at a typical value of 3 MHz for the TL071, and the differential voltage will therefore increase.
The TL071's slew rate will limit the output voltage swing at high frequencies, but at +/- 15V rails, it can do full voltage (about +/- 12V) up to 100 kHz, where the AC gain should be 30 V/V, and the swing in differential voltage for +/- 10V output swing will be +/- 330mV.
The TL071 data sheet http://www.ti.com/lit/ds/slos080n/slos080n.pdf?&ts=1590006908444 (http://www.ti.com/lit/ds/slos080n/slos080n.pdf?&ts=1590006908444) is quite comprehensive, and should answer your questions for a typical op-amp.
-
What the Fox says...and this dc model for an opamp.
For dc offset, there is the systematic offset (which with proper design...is zero) and random offset (random from chip to chip).
As you can see in the model, input bias currents are not necessarily equal...they too have an offset (current).
-
So, I would like to know the physical reason that causes Vd to be non-zero when Avo is finite (for example, does it caused by imperfection of transistors? If yes, what kind of imperfection is that?)
Thank you!
Yes. Imperfections in the transistors is are the dominant reason for your garden-variety opamp.
I spent my life designing CMOS circuits, so I will stay in my lane.
For MOS, the dominant component of offset is the difference in threshold voltages of the input pair. Mobility differences will also play a role.
-
So, I would like to know the physical reason that causes Vd to be non-zero when Avo is finite (for example, does it caused by imperfection of transistors? If yes, what kind of imperfection is that?)
It has nothing to do with imperfections of the transistors. It's a matter of cause and effect -- there needs to be some difference between the input voltages in order to get any output voltage at all. The larger the gain, the smaller that difference needs to be for a given output voltage.
As for why the gain isn't infinite -- well, it's just not physically possible. Think about it: you're expecting the output to be some non-zero voltage V with zero input. How is it supposed to know what V is?
-
Opamps have finite gain because they consist of a finite number of simpler single- or few-transistor amplification stages, and all of the known ones so far happen to have finite gain :P
Opamps have finite gain at AC to remain stable. They kinda work by moving their output up or down at a rate proportional to Vd, until Vd is so small that they become limited by open loop gain. Even if one had unlimited open loop gain, you would still spend eternity waiting for it to fully settle.
-
So, I would like to know the physical reason that causes Vd to be non-zero when Avo is finite (for example, does it caused by imperfection of transistors? If yes, what kind of imperfection is that?)
It has nothing to do with imperfections of the transistors. It's a matter of cause and effect -- there needs to be some difference between the input voltages in order to get any output voltage at all. The larger the gain, the smaller that difference needs to be for a given output voltage.
As for why the gain isn't infinite -- well, it's just not physically possible. Think about it: you're expecting the output to be some non-zero voltage V with zero input. How is it supposed to know what V is?
Incorrect.
You are confusing input-referred offset to output-referred offset. Offset is never specified as the latter--it is always "input-referred." Look at the model I posted.
As TimFox stated (and I paraphrase), input offset is the differential input voltage required to achieve an output voltage of zero.
So, lets say that you have a perfect differential stage with an open-loop gain of 10. With a differential input voltage of zero volts, the output will be 0*10=0.
Same answer if the gain is infinity.
Now, if you have an offset in the differential stage, say +1mV, then in order to get a zero volt output you will have to input -1mV irrespective of the open loop gain.