Routing power - traces length and bulk capacitor placement

[newtekuser]

I am using a 2 layer board for my project where the bottom layer is ground (mostly solid except for one jump that I need to make from the top to bottom), the top layer is used for signal and power. Until recently I was routing power using a copper pour on the top layer, but felt that the signal traces were just too close for my linking to the power pours and offering less control (not that I have anything high speed, mostly i2c stuff), so I ditched the copper pours and routed power using a thick 1mm trace that spans along the perimeter of the PCB. From there I pull power to each individual component with thinner 0.6mm traces. The PCB is 79mm x 67mm so the power trace is pretty long.
I do have a bulk 100uF capacitor on 5Vin and thinking that I should be adding additional bulk capacitors at regular intervals (what distance?) along the power trace to protect from transients. Or should I go back to using a copper pour for power?

The only constraint I have is 2 layers, so I can't go higher than that.

[bson]

That's not a large board, and even a trace going around the perimeter isn't long.  And be careful with the perimeter, a small PCB edge cut offset may impinge on a trace there, so make sure to accept a small margin for error.  What kind of switched current consumption do you expect? 100µF is already pretty bulky unless you drive a motor or something, but if so I'd rethink the design (separate the drive supply from control circuitry supplies).  Do you need anything more than just a little decoupling close to the supply pins?

[newtekuser]

That's not a large board, and even a trace going around the perimeter isn't long.  And be careful with the perimeter, a small PCB edge cut offset may impinge on a trace there, so make sure to accept a small margin for error.  What kind of switched current consumption do you expect? 100µF is already pretty bulky unless you drive a motor or something, but if so I'd rethink the design (separate the drive supply from control circuitry supplies).  Do you need anything more than just a little decoupling close to the supply pins?

I am actually driving a 12V bi-polar stepper motor, total current draw for the entire board at any point will be 1A max with the motor running. The motor runs off a custom made boost converter. At its output I have another 100uF cap going into the motor driver IC (motor pins).
So I have total of 2x 100uF electrolytic caps on the board, one on main 5Vin and another on the 12Vout. All ICs on my board have 100nF ceramic decoupling caps.

[PGPG]

I am using a 2 layer board for my project where the bottom layer is ground (mostly solid except for one jump that I need to make from the top to bottom), the top layer is used for signal and power.

I use the same strategy except:
I use 0R instead of breaking GND.
I didn't tried to route power with zones.
Not used space at top I fill with GND adding many vias to bottom GND.

I use 1mm for 200mA. For 1A current I would be trying to use 2mm or wider tracks. Fortunately I don't have such currents.

I have shown example of my PCB at KiCad forum:
https://forum.kicad.info/t/approaching-pcb-track-routing-for-a-newbie/36302/8
All vias at this PCB are GND.

[newtekuser]

I am using a 2 layer board for my project where the bottom layer is ground (mostly solid except for one jump that I need to make from the top to bottom), the top layer is used for signal and power.

I use the same strategy except:
I use 0R instead of breaking GND.
I didn't tried to route power with zones.
Not used space at top I fill with GND adding many vias to bottom GND.

I use 1mm for 200mA. For 1A current I would be trying to use 2mm or wider tracks. Fortunately I don't have such currents.

I have shown example of my PCB at KiCad forum:
https://forum.kicad.info/t/approaching-pcb-track-routing-for-a-newbie/36302/8
All vias at this PCB are GND.

I used the Kicad PCB trace calculator to give me a good buffer and 1mm seemed more than adequate for my requirements. However, after inputting some outrageous values into the calculator I start to question whether I'm using it wrong, or if it's dead wrong.

[bson]

What seems wrong?

It comes up with R=1.5e14Ω, V=8e14V and 5.6e15W dissipated for a 1mm wide, 1oz trace.

What do you think it should be?

Or do you think it should tell you the trace would have vaporized long before this?

[newtekuser]

What seems wrong?

It comes up with R=1.5e14Ω, V=8e14V and 5.6e15W dissipated for a 1mm wide, 1oz trace.

What do you think it should be?

Or do you think it should tell you the trace would have vaporized long before this?

I'm looking at the values it gives for "Trace Width (W)" and "Trace Thickness (H)", they don't seem to vary much even after increasing the current to 7A.

[ArdWar]

Your gazillion inch length is what causing it to go nuts.
It only calculate radiative heat dissipation. At your values it's only 0.56W/inch, which is reasonable for 100C Trise

[newtekuser]

I found the answers to my questions reading from "PCB Design and Layout Fundamentals for EMC" by Roger Hu (ISBN 9781082079252).

- the value of bulk capacitor needs to be at least 10 times greater than the sum of all values of de-coupling capacitors
- traces should be shorter than the diagonal dimension of the board

In a nutshell, will place bulk caps at each interval along the large power trace once the distance becomes greater than the diagonal of my PCB.

As a bonus tip for my case:

- power and clock traces should not be routed close to the PCB-edges, otherwise they should be accompanied by a guard ring on the PCB trace (will add top ground VIAs connected by traces around the perimeter of the PCB).

I'll also eliminate the break in the GND plane as PGPG suggested by using 0R resistors to jump over traces on the top layer.

[Vovk_Z]

I have to add that proper routing and proper capacitor types help more then 'an interval' or large bulk capacitance value.

[newtekuser]

I have to add that proper routing and proper capacitor types help more then 'an interval' or large bulk capacitance value.

Right, I know I'm just scratching the surface
I found more info on trace routing from a public Intel doc: https://www.intel.com/content/www/us/en/docs/programmable/683073/current/single-ended-trace-routing.html

[Doctorandus_P]

That intel document assumes signals with a 1ns risetime. I think you have some headroom before your I2C signals get into trouble.

And for the rest, same rules as always:
* Plenty of decoupling caps near each IC to take care of the high frequency stuff in the power lines.
* A good GND plane to serve as a reference for all signals, the shortest return path and lowest impedance for all signals.
* A bulk buffer cap. This is mostly a medium to low frequency buffer, because the power wires to the PCB have much more inductance then the much shorter PCB tracks. It's location is not very critical, but it's optimum location is in between the power input connector and current hungry parts of the PCB.