It's not at all useless; higher resolution, high speed ADCs tend to have really poor performance specs, relatively speaking. Example: you might find a series of ADCs rated for 12, 14 and 16 bits in the 65, 80, 110, etc. MS/s range. In a given speed class, the 12 bit one will have ~11 ENOB, the 14 bit will have ~12 and the 16 will have maybe 12 or 13. That's taking ENOB as total error: noise, INL and DNL, all together. What possible point is there? These typically have low DNL, meaning they are good for resolving AC signals -- the THD+N of a sine wave, or THD+IMD of a multitone signal, is very low, 0.5-2 bits worth, independent of the number of bits. Naturally, high sample rate ADCs are most often bought for ultrasound and SDR type applications, where AC signals are indeed the purpose.
It's all about signals. Think to yourself: how can I better rearrange this measurement, so that it is performed by difference against another known or measured value? How can I convert the signal to an alternating or varying signal and perform AC analysis on it (a chopper amplifier is a good analogy)?
The biggest problem with an 8 bit ADC will be establishing the baseline between those relatively lumpy bits, and dithering out their corresponding noise. And note that ENOB goes up logarithmically with averaging, so to go from 8 bits to 12 bits requires at least 16 averages, and from 12 to 16 requires 16 averages of those or 256 samples.
Subtractive dithering would be a good idea. You'll likely not have a noisy enough signal to achieve dithering by itself (the baseline reading should vary up and down by a few counts peak to peak, to do a reasonable job), so you'll have to add noise; so, you might as well take advantage. You can add this from a DAC, and since you know what value is being added, you can subtract it from the reading (bit-aligned according to the gain ratio between ADC readings and DAC settings), and get much better noise reduction. The DAC output should probably be something without a pattern, such as a pseudorandom number generator (a 16-32 bit LFSR would do a fine job, and be easy enough to implement in any modern processor, as fast as the ADC/DAC needs it).
If necessary or desirable, you can perform calibration on the system, by setting a couple input values (precision voltage reference?) and reading them. You can also adjust the subtractive dithering process to null its gain; normally, the additive amount is a dozen or more counts (so, ~4 bits worth), so the baseline "0" reading should only ever be -0.5 to 0.5 counts (taking the fraction as 1.0 counts, as read from the ADC, after subtracting the difference which is bit-aligned for, say, 4.4 bits for a total 8.4 (12 total) bits per sample). You can adjust the gain and offset of the summer to achieve this.
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So, this is good to know and all, but in the grand scheme of things, you definitely want to go out and buy an external ADC, if this is your situation and you don't need anything special. The performance specs are always better than integrated ADCs (lower error, lower noise, higher sample rate), and the cost is lower than all the stuff talked about above (maybe not if you reduce the dithering process to a single op-amp and some support parts, but anything more than that?..). Really, the only reason they put those ADCs in MCUs is convenience, for the simple applications where that's all you need. They aren't generally intended for high bandwidth or precision work (dsPICs being a possible exception, having pretty good sample rates).
Tim