Author Topic: Package drawings with min max pitch  (Read 577 times)

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Offline DroneBuster

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Package drawings with min max pitch
« on: December 27, 2016, 02:47:01 pm »
Hello,

I was drawing footprint for IRS2334 SOIC package (http://www.infineon.com/dgdl/irs2334pbf.pdf?fileId=5546d462533600a40153567aa9fe280b) and I was amazed that pitch was given as MIN 1.018 mm and MAX 1.524 mm. What dimension should I use for drawing pitch? Use average which is 1.271?
 

Offline icecold

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Re: Package drawings with min max pitch
« Reply #1 on: December 27, 2016, 03:03:10 pm »
According to your calculation and wikipedia I would use 1.27
https://en.wikipedia.org/wiki/Small_Outline_Integrated_Circuit
 

Offline T3sl4co1l

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    • Seven Transistor Labs
Re: Package drawings with min max pitch
« Reply #2 on: December 27, 2016, 08:21:56 pm »
Eww, shitty underdimensioned drawings.

They don't follow IPC convention on symbols (A = height, C = width, D = length, etc., or whatever it is), either.

Presumably, what they mean is not that each pin gap can be that range, independently, but that that's the maximum for any pin, and that each pin (relative to an unspecified datum) has to land within that range of its ideal placement, given the typical (1.27mm) pitch.

This is most often specified using IEC drawing conventions, where the pins are shown relative to a datum, their ideal locations given by REF dimensions, and the tolerances added to features (relative to the datum) with labels.  This is better than the above condition, because one can specify whether the tolerances apply to most- or least- material condition (MMC/LMC), and what the statistics of those dimensions are (the most likely error for a pin, is that it's bent; so the pin angle can be specified, or the positional tolerance of the tip of the pin).

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
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