BJT in parallel. Can this simple simple schematic work?

[JhonStan]

Hi,when I first saw these software the first thing I thought was "it sucks". Then now I appreciate it very much. As a pure simulator I think it is one of the best. I drew up a diagram because I was curious to see how the BJT in question behaved. It seems to me a good recult but I would also like your opinion as a veteran and if possible a solution. Although it has a good gain, the purpose of this is primarily to manage the current then as a final. I was just undecided whether to allocate a resistor for each single emitter or a single one for all five BJTs. I chose the second solution but in case of breakage of one of the transistors it could have an overload of the others. What do you think?

[TimFox]

As a simple simulation, the emitter resistors can help make this work.
Without these "balancing" resistors, one or more of the NPNs will "hog" the current, since they aren't identical.
I have seen similar circuits used on very high power linear power supplies, with a fuse and resistor in each emitter for many NPN transistors.
However, if you want to see how well the circuit works in simulation, you need to vary the parameters (beta, etc.) between the transistors, since your circuit seems to use absolutely identical devices (not physical).

[Benta]

The emitter resistor topology works very well when paralleling power transistors for DC or low frequencies (eg, audio).
As a rule-of-thumb, a 0.3...0.5 V drop over the emitter resistors at maximum current is a good starting point.
You'll need to do a lot of work on the base biasing resistor network, though.

[bd139]

Look up emitter degeneration. Adding a resistor to the emitter is a negative feedback mechanism that decreases gain slightly to increase stability and linearity. The actual function is to reduce the transconductance (gm) of the transistor as biased slightly. This as a side effect makes the circuit's characteristics depend on the ratio of emitter resistor to load rather than the transistor as that is really unpredictable. This has an impact on input impedance as well so if you need source matching it requires some fiddly mathematics.

Anyway not sure what you're building there but it's better to stack a couple of lower gain stages than have one massive chunk of gain at that sort of frequency.

If it's RF sort of frequencies, and small signal, then these are very reliable, stable and well engineered: http://w7zoi.net/bidirectional_matched_amplifier.pdf  (just built one direction, not both)

[T3sl4co1l]

A few things to note:

- As shown, you have "suicide biasing".  In sim, hFE and temperature are fixed; in practice, they will differ between parts, and temperature will vary over time.  This is harder to simulate.  (SPICE was developed for working with integrated circuits, where equal temperature is a safer assumption than for board-level components!)

All models in a sim are perfectly matched, so you'll get perfect matching regardless of topology, of course.

You can start to get a more realistic idea of this, by customizing the models for each part; or using a Monte Carlo simulation (varying hFE or whatever).  I don't know how to do this in LTSpice offhand, but check out further reading along these lines, ought to be something useful out there.

- This is easily fixed by putting a divider resistor below R2, and optionally, tying its top end to collector(s) rather than +V (so it gets some DC negative feedback from the output).  Often some (AC) feedback is done intentionally this way as well, as "neutralization", i.e. using an intentionally relatively low value for R2.  (That's not actually neutralizing any reactances, it's a resistance, obviously; it's really just flattening the amplifier's response, trading gain for stability.  It also burns some power, as the value usually needs to be low enough to steal a substantial fraction of the output [some percent], which might not be ideal if you're going for a high efficiency amplifier.  So, it trades off several things together.)

- Nodes are ideal, so there's no stray inductance between transistors, or capacitance to ground.  You may see a stable simulation, which isn't even constructible in real life because zero stray inductance and capacitance implies a circuit of zero dimension.  The fact of the speed of light, manifests as equivalent inductance and capacitance in a lumped-element circuit like this.

If your transistor models have package parasitics included, that's a start; you can further enhance the model by adding L and C between transistors, corresponding to the particular PCB layout you intend to use.  (So, depends on topology, if you've got a block of 'em in parallel, or routed in a (linear) chain, etc.  Coupling between inductors would also be interesting to model, but quickly gets very complicated to express -- and measure!*)

*There are, in fact, tools to do this; but they're all enterprise-grade, AFAIK.  Example, Ansys has a PCB field solver tool, which extracts a coupling matrix corresponding to a real physics-based model of the PCB.  It also costs six digits $...  (Probably, the 4-5 digit$ ADS and such, can do the same as well?  I'm not very familiar with them, alas.  Great way to go, though, to construct that pesky "10n" on your sheet -- which might be a mere cm of trace length, but what exact length and width, now, that's the question!)

Anyway, adding some strays, hand-wavingly representative of some layout you have in mind, might not be a bad idea for getting some idea of bandwidth and stability.

Which, as for that -- all the amplifiery things we do in RF, have to be constructed in the sim.  Read up on the definition of source and load ports, reflectance, etc., and construct bridges (or postprocessor expressions to the same end -- in AC analysis anyways, else you'll have to construct the full thing for transient analysis) to measure incident and reflected power, phase shift, etc.

Tim

[Wallace Gasiewicz]

I have seen a lot of these things in 10 meter (11 meter) radios.
In practice and at the present time, they are using MOSFETS, mostly IRF 520. I have repaired these things, some of them use EIGHT 520s.
There are resistors on the gates of the FETs, about 5 ohm and the input and outputs are transformers. Input and output matching is very very important.
Heat sinking is also very important. And fans....etc
If there is not a resistor or some other sort of oscillation damper (maybe a ferrite bead) on the inputs of each FET or transistor, these things go up in very interesting smoke.
The BIAS on each FET is very important, overdrive one and ....smoke. FETs are somewhat "matched"
If they are slightly overdriven they go up in smoke.
If the PS voltage is not correct, they go up in smoke.

If you wish to have some schematics, PM me. They are really not that complicated.
I realize that you are using a GHz rated transistor not a MHz rated FET, but your pics indicate that you are using the transistor at 10 MHz, or am I reading something wrong?
Also you are not dealing with high power. But I think my observations apply to your lower power amplifier.

[JhonStan]

Thanks to everyone for the answers and for the links, I was warned about the stability problem using BJTs in parallel. However, I was hoping that being used far below their rated current this problem could be very limited.
I also accept the advice to reduce the gain. In fact it is very high. Being seen as a final stage I can give up the voltage gain if I keep the current gain. Basically used as a current buffer (is the term correct?).
The problem is that even working with the dividers with the resistors I see that by lowering the voltage gain I obviously also reduce the current gain.
The need to use RF components with high fT with respect to the set frequency of use (ie 10Mhz) derives from the need to have practically zero phase shift. To maintain this feature I need very high fTs.

[magic]

If one transistor in the set is 1°C hotter, its Vbe for the same Ic decreases 2mV, which corresponds to ~7% increase in Ic for the same Vbe if no individual emitter resistors are present.
If 7% more power dissipation is enough to maintain 1°C difference, the transistor will stay that way. If it's more, it will heat up further and take an even larger share of load current and thermal runaway may occur.
If it's less, the transistors will tend to equalize, except for the effects of production variation in Vbe (± a few mV typically).

[JhonStan]

Ok you have convinced me that this is not a good idea. Thanks.