EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: XtraLumens on September 23, 2020, 02:34:46 am
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From my understanding, there are two models used to asses ESD sensitivity: HBM (component level) and IEC (system level). ESD protection can be implemented via on-chip and off-chip design measures. Is it possible to pass IEC testing only relying only on on-chip ESD protection measures?
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What constitutes an off-chip design measure? Some circuits fundamentally will not function without a minimum degree of design, for example the use of ground planes. But ground planes afford some degree of ESD immunity.
If you mean, simply not going out of your way to add ESD-specific components, there are certainly some circuits that can succeed that way. A fairly trivial case is simply using devices that offer high ESD ratings in the first place.
Whether any particular circuit can? Well, that'll require a lot more information about it. And not just the circuit, but software running on it as well, if applicable.
Tim
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Maybe. You could pass it, but it depends on the IC in question. IE, an RS485 transceiver could have the necessary protection to pass it. A low input bias current opamp will probably not pass. It also depends on your layout, enclosure and other factors.
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Thanks for the responses.
From the literature I've been reading, on-chip protection measures usually are harden to HBM standards, whereas off-chip protection measures (e.g. transient diodes) are rated to IEC system level standards. It has been stated that the response time of a HBM protection circuit will not turn on in time if an IEC level discharge were to occur and possibly fry the sensitive IC. This is because the IEC waveform rise time is ~0.7- 1 ns, where as the HBM waveform rise time is around 25 ns. I really want to understand the mechanisms behind this.
It seems that in order to ensure robust protection (especially to level 4), the use of off-chip protection measures may be necessary for system level ESD protection.