I don't think its a great idea and would look for alternatives first. One thing that you could do is to reduce your trace widths on low current pins- they all seem rather large. This could give you some layout room to squeeze traces to make that connection.
A via on each side and a trace under the iC would be preferable. Though usually that thermal pad is via'd to both sides I don't know what those pins are w/o schematic but do they require a short run?
The IC die is bonded to to that slug on the inside, probably mostly in the center, its a pretty small die. By having that gap, you have a thermal gradient across with hot and cold spots.
Are you operating the parts at its maxes as far as power goes, etc.
The other issue is that you're really depending on solder mask quality next to tinned area to make it work, not completely planar and probably not a 100% yield kind of deal.
Also, those under IC thermal pads are supposed to be full of Vias to aid thermal conduction to the other side, etc.
The data sheet has some reasonable looking layouts included.
My 2 cents