Electronics > Beginners
PCB layout advice needed: vias vs long tracks for power and data tracks
(1/1)
V_King:
Hello,
I am routing a simple 2 layer PCB and have one dilema:
There is an ADC (AD7606) and MCU and there is good 20 lines between each other to control settings and transfer data in parallel. The problem is that ADC has Vdd in the middle of the data tracks.
I have the following options:
1. route shortest data tracks and a long power line around all data tracks
2. run the power supply track through vias
3. run the shortest power track and take half of all data tracks through vias to the back and then back up to MCU.
the ADC max current is roughly 20mA. I am using 3V3 logic.
For me, mechanical engineer, vias are weird and misunderstood world. So I would appreciate if somebody could explain each option drawbacks and benefits.
I am running parallel data transfer to avoid introducing noise into ADC so there are no high frequency switching tracks. I will be sampling with ADC up to 10kHz.
Thanks
iMo:
The fast edges of the signals are important when talking interference/crosstalk/coupling/noise..
The vias introduce a small inductance. Also right angle bending of a trace is not recommended.
With power and ground traces always use several vias to lower their inductance.
I would go with 2.
T3sl4co1l:
Electrical ground works the same way mechanical ground works. The further off ground something is, the springier or softer its ground reference. Compare machine bolted to concrete pad, versus teetering on top of a flagpole. Works the same way here, with beams replaced with traces, beam cross-section replaced with trace width and height over the ground plane (wider and lower is stiffer), and beam length equal to trace length, and the resonant frequencies being shifted up a few half dozen orders of magnitude (nanoseconds vs. seconds, say).
The main quirk is that, in electronics, we can make a ground at any voltage -- mechanical analogies to capacitors and inductors are somewhat imperfect. With enough capacitors, we can make an elevated node behave near enough to "ground" for all intents and purposes (whereas this is harder to do with, say, skyscrapers, that tend to wobble in the wind).
What you want to do for signal traces is, fan them out around the supply pins so you have space to put a bypass cap in there. The bypass cap goes from the VCC pin to GND. GND is poured on the bottom side, so it can link back to the chip through vias on GND pins. Power is routed to the VCC pins wherever it fits, but be careful not to cut up the ground pour in the process -- a trace leaves negative space in the pour around it. Prefer routing (signals and VCC) on top side, with bottom side reserved for GND, and short crossing traces as needed.
Put lots of vias between GND pours on both layers -- this is analogous to building a parallel pair of trusses, and using just a few stringers between them for stiffness (hardly does anything), versus regular diagonal bracing (highly effective). Analogously, you don't need a massive swarm of vias, just one every so often (10-30 mm?) will do, plus any hot spots (three or four at trace crossings, one at the end of a peninsula, etc.).
Tim
Kasper:
2 with plenty of vias.
If you use decoupling capacitors (most IC datasheets recommend these), place them on same side as IC, close to IC power and gnd. When it is hard to route to power and gnd without vias, it is common to place Vcc side of cap very close to Vcc of IC and gnd side connected to gnd of IC through via(s). With low impedance (short and wide tracks).
How many vias? Look up current carrying capacity of vias to get a rough idea of the minimum. Add more than minimum for safety factor and noise supression.
V_King:
thanks all for the responses. #2 is the winner. Tried quickly routing the power trace with two vias, but KiCAD does not allow and either removes the track or the via to have one current path. Tomorrow will have more tome and will try googling how to change settings for that.
Navigation
[0] Message Index
Go to full version