phase detect circuitry

[promach]

How is clk_dcc generated from the following phase detect circuitry ?

[ataradov]

It shows it right there with timing diagrams.

They use either clk0 or clk180 as a clock for the D flip-flop. And the output of the flip-flop controls which one is used as an input.

DFFs are often used to generate a 50/50 duty cycle, but the issue is that the output clock frequency is half of the source clock. This way they maintain the same clock frequency, since they use alternating phases as a clock source.

This is pretty clever. Not sure how common this trick is, but I'm definitely stealing it.