Author Topic: Phase Frequency Detector without dead zone  (Read 2083 times)

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Offline promachTopic starter

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Phase Frequency Detector without dead zone
« on: June 29, 2019, 12:01:30 pm »
How does the two inverter delay stage in Figure 6.14 on page 265 of Design of CMOS RF Integrated Circuits and Systems helps to eliminate dead zone in Phase Frequency Detector ?











 

Online David Hess

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Re: Phase Frequency Detector without dead zone
« Reply #1 on: June 29, 2019, 04:01:40 pm »
I think what is going on is that the delay to clear prevents a race condition where neither output is active in the dead zone.  Instead, both outputs become active and the difference in timing between the two outputs determines the net output current.
 

Offline Benta

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Re: Phase Frequency Detector without dead zone
« Reply #2 on: June 29, 2019, 05:42:45 pm »
In a PFD, you need to feed the loop filter to keep the VCO stable. With an uncontrolled dead zone, you'll have a number of positive spikes, followed by a number of negative spikes, which causes jitter at the frequency of the loop filter response (=low frequency).
By making certain that the output of the PFD always outputs alternating polarity pulses at input frequency when locked, the jitter frequency is equal to half the input frequency, which means it much higher than the loop filter cutoff frequency and thus negligible.

Smart design, by the way.
 

Offline promachTopic starter

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Re: Phase Frequency Detector without dead zone
« Reply #3 on: June 30, 2019, 02:43:50 am »
how does delay block after the 4-input NAND circuit determines the minimum width of the up- and down-pulses ?
 

Offline hamster_nz

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Re: Phase Frequency Detector without dead zone
« Reply #4 on: June 30, 2019, 06:22:00 am »
If you can think about these two questions, you will have your answer...

How long does a signal take to propagate though a basic logic gate?

What is the function of the signal that is being delayed? What does it do?
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline promachTopic starter

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Re: Phase Frequency Detector without dead zone
« Reply #5 on: June 30, 2019, 06:35:47 am »
The book version adapts the original version (Cell-Based Fully Integrated CMOS  Frequency Synthesizers) with slight modification.

Any idea why the book version does not require the feedback signal of DOWN signal ?

 

Offline hamster_nz

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Re: Phase Frequency Detector without dead zone
« Reply #6 on: June 30, 2019, 07:23:32 am »
The book version adapts the original version (Cell-Based Fully Integrated CMOS  Frequency Synthesizers) with slight modification.

Any idea why the book version does not require the feedback signal of DOWN signal ?




Did you notice that the outputs are not named the same - the original picture has bit UP and DOWN being active low, and the later has active-high UP and an active low DOWN?
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline promachTopic starter

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Re: Phase Frequency Detector without dead zone
« Reply #7 on: July 01, 2019, 07:46:55 am »
How does the PFD deadzone-free circuit ensures that the SR latches do not enter metastable state ?




I do not understand how the two SR latches in the middle region works. What are those two latches for ? Besides, what is the purpose of the 4-input NAND gate ?


Quote
The 2 inverters are needed to provide delays for the UP and Down current source to turn on. 

We may use more even number inverters stage if needed to ensure the current sources are turn on.

The book author told me the above. What does it mean by "delay reset to guarantee min pulse width" ?

« Last Edit: July 02, 2019, 08:16:33 am by promach »
 


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