Electronics > Beginners
Phase Frequency Detector without dead zone
promach:
How does the two inverter delay stage in Figure 6.14 on page 265 of Design of CMOS RF Integrated Circuits and Systems helps to eliminate dead zone in Phase Frequency Detector ?
David Hess:
I think what is going on is that the delay to clear prevents a race condition where neither output is active in the dead zone. Instead, both outputs become active and the difference in timing between the two outputs determines the net output current.
Benta:
In a PFD, you need to feed the loop filter to keep the VCO stable. With an uncontrolled dead zone, you'll have a number of positive spikes, followed by a number of negative spikes, which causes jitter at the frequency of the loop filter response (=low frequency).
By making certain that the output of the PFD always outputs alternating polarity pulses at input frequency when locked, the jitter frequency is equal to half the input frequency, which means it much higher than the loop filter cutoff frequency and thus negligible.
Smart design, by the way.
promach:
how does delay block after the 4-input NAND circuit determines the minimum width of the up- and down-pulses ?
hamster_nz:
If you can think about these two questions, you will have your answer...
How long does a signal take to propagate though a basic logic gate?
What is the function of the signal that is being delayed? What does it do?
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