Author Topic: DS Logic Analyzer what is relation between Mhz samples and uC clock  (Read 363 times)

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Offline sairfan1Topic starter

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I'm quite new to using DS Logic analyzer, at the top of DS Logic Application there is a drop down to choose MHz, I want to know how do i choose, what are the basis for choosing MHz
For example I'm using PIC uC 16F18624 to debug SPI, PIC uC datasheet explains clock for Master mode it could be set to Fosc/64, Fosc/16 and Fosc/4 where I'm using uC @ OSC 4Mhz

Lets see only one scenario i choose Fosc/16, when I debug SPI using DSLogic, every time i change Mhz from drop down like 1Mhz up to 2,4,5,10,20Mhz always I get different values on debug decoder
Above all I never get the values that are expected. (0xC3), I choose other configurations as well to set different SPI clock.
BTW I'm communicating with NRF24L01+ to write and then read back the registers.

 

Offline RAPo

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Look in the manual for fig1.2 (around page 8).
That figure describes the two fields. MHz the sample rate.
In 2.3.2 the sample rate is further explained.

As a rule of thumb, you will need to sample digital signals at least 4 times faster than their bandwidth.
Salea has a good description here
 
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Offline pcprogrammer

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The problem with sampling with a logic analyzer is that depending on the sample rate (I assume expressed in MHz here) there can be shifts in when it thinks it has the edge of the SPI clock.

Lets say your SPI clock is 250KHz, which means that the clock changes level every 2us. (Period time is 4us) When you sample with 1MHz it only takes a sample every microsecond. This means there can be a delay between the actual SPI clock change and the sampling software seeing it change. This can lead to not seeing the correct values being send on the data line, because to be correct it needs to be looked at on the exact moment the SPI clock changes.

So using a higher sample rate improves on this.

The fact that with the highest sample rate you don't get the expected values might mean that the PIC uC is not sending it.

Offline pcprogrammer

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Another observation of your attached pictures show something wrong with the top to lines of the sampled data. They look very similar as if you are sampling the clock signal twice instead of the CLK, MISO and MOSI signals.

For 0xC3 you should see a signal with two clock cycles high, four clock signals low and two clock cycles high on the data line.

It depends on your SPI settings on which clock edge the data is clocked. Look up the different SPI modes that exist with clock polarity and clock phase.

Offline Doctorandus_P

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First, a weird thing. The part of the time scale shown is apparently 60us, but it shows 10 subdivisions. That is a bit of a stinker.

When sampling with a Logic analyser, you ideally want your sampling frequency 10x or more higher then the rate at which your signals are changing. You do not only want to observe the data, but also timing differences between the clock and the data. With a higher sampling frequency, you get a higher resolution to measure such differences. At the zoom levels shown in your screenshots, you can not see the timing between clock and data. You have to zoom in further to see that. I am not familiar with the DS Logic Analyzer, but when you zoom in, then usually there is some indication of what the actual samples are.

For SPI there are also different combinations for sending data. Data can be sampled on either the rising or the falling clock flank. And data can be inverted too. You have to set the Logic Analyzer to the same settings as which you are sending the data with.
« Last Edit: May 30, 2024, 12:07:13 pm by Doctorandus_P »
 
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Offline sairfan1Topic starter

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I'm trying to write NRF24L01+ registers and then read back to ensure if it was written correctly, I'm quite sure that SPI related parameters were correct.
 


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