Please identify amplifier topology

[13hm13]

Please identify amplifier topology

Here:



Thanks!

[magic]

Common base, what did I win?

BTW, R4 seems too high if you want the input to be at ground exactly.

Also, DC voltage gain of this stage is very high, I don't think it will bias correctly without some sort of negative feedback from the output, but the output is AC coupled, so

[13hm13]

Common base, what did I win?

BTW, R4 seems too high if you want the input to be at ground exactly.

Also, DC voltage gain of this stage is very high, I don't think it will bias correctly without some sort of negative feedback from the output, but the output is AC coupled, so

Thanks!   R4 may be a variable Bourns pot in my proto for that ckt. It's part of an audio i/v design from years ago. Excellent sound once tweaked.
What about any hints of "cascode" in that ckt?

[TimFox]

Common base, what did I win?

BTW, R4 seems too high if you want the input to be at ground exactly.

Also, DC voltage gain of this stage is very high, I don't think it will bias correctly without some sort of negative feedback from the output, but the output is AC coupled, so

Thanks!   R4 may be a variable Bourns pot in my proto for that ckt. It's part of an audio i/v design from years ago. Excellent sound once tweaked.
What about any hints of "cascode" in that ckt?

There is absolutely no cascode in that circuit.  In a BJT cascode, the collector of a "lower" transistor drives the emitter of an "upper" transistor, and the output comes from the collector of the upper transistor.
"Cascade" is a generic term, but "cascode" has a specific meaning.

[Calvin]

Hi,

that circuit runs under the name ´Jocko´ and has its own thread in the DIYaudio forum.
As mentioned before its a common Base/Gate/Grid structure that basically functions as a impedance and level matching circuit.
It presents the DAC -which is a not an overly good current source with only a couple of hundreds of Ohms and level-varying output impedance- the required low input impedance at 0V and offers a much higher output impedance and voltage compliance.
It is well suited to current sinking DACs featuring a offset current.
Changing to a PNP topology it is well suited to current sourcing DACs like the popular PCM179x series from TI.
In that case the Q3 current source and the positive supply line may be omitted with, feeding the DAC´s current only into the emitter of Q2 (see attachment)
With a simple bipolar or JFET as Q2 THD will be limited to about -60dBFs, either due to the Base current or the Source input impedance beeing not low enough.
THD distribution is nicely falling with a dominant H2.
The addition of Q3 mitigates the Base current problem and reduces the already low emitter impedance.
The attached schematic is dimensioned for the PCM1792/1794 DACs of TI which sources -6.2mA +-3.9mAp.
For PCM1795 featuring lower currents the schematiics need a slight redimensioning.
For DACs wo offset current like PCM63, TDA1541 etc. a current source (similar to Q3) towards the positive supply needs to be reintroduced.

Further improvements could be a current mirror instead of the collector-resistor R3.
The CM improves the almost non-existing PSRR, reducing the requirements on the power supply lines.
The CM would mirror the signal into a constant current source towards the positive supply, that should cancel the offset current precisely.
The i/V conversion would happen with a Resistor Riv (and a bandwith limiting cap Civ) between the CM and CCS to 0V.
The current source may be improved again in that it could be replaced by another current mirror (Q4, Q5 Duals) with its output leg connected to Riv and its input leg going to the Drain of a NJFET that´s Gate is controlled by a DC-servo-OPAmp.
This way the DAC´s offset current can be precisely nulled, so that the output voltage over Riv is truely free from dc offsets.
Also, using the NJFET allows the output of the DC-Servo-OPAmp to be 0V referenced and close to 0V.
This ensures that the servo functions right from the start-up.
The NJFET must have an Idss larger than the DAC´s offset current.
It´s source resistor (R18) may be trimmed such that the output voltage of the circuit is ~0mV with the NJFET´s Gate shorted-to-0V.
Transistors can be matched Duals like BC847/857.
Even with simple current mirrors (the ´cascoded´ Wilsons tend to oscillate) the circuit functions very well ... with THD reaching down to -100dBFs, H2 dominating, and nicely falling distribution.

Adding the shown diamond Buffer preserves the excellent data, drives attached loads and cabling easily and one can use the same matched DUAL transitors.
For Q10, Q11 medium power transistors likem FZT651/751 or ZTX849/949 suit well.
In case of too high heat power losses, omit with Q2a/Q4a and replace Q6, Q2b and Q4b with the same medium power transistors used for the Buffer, or reduce the supply lines to +-9V.

Sonically - Yeah, knowing this could open a can of worms in this forum - these simple I/V structures perform very well, showing a degree of ´authenticity´ most OPAmp based I/Vs don´t deliver.

regards
Calvin

[magic]

Yeah, this makes more sense now.

Note that in both schematics the collector of the input transistor is loaded with a relatively small resistor. In OP's circuit, it is only loaded with another transistor's collector, at least at DC. This gives very high impedance and very high voltage gain - it would be practically impossible to match these collector currents so that neither transistor is saturated and the output is centered at 50% of rail voltage.

[magic]

Even with simple current mirrors (the ´cascoded´ Wilsons tend to oscillate)

I can't say I have ever used a Wilson mirror, but I thought that they are supposed to be stable. I think I have even seen commercial opamp schematics which showed a pair of Wilson mirrors at the gain node (yep, LT1363).

Maybe it doesn't like the capacitive load of Civ, I wonder if a simple isolation resistor between the collector node and Civ/Riv would help. Failing that, there is an extremely widespread trick which reduces base current errors - driving a simple mirror with an emitter follower.

[Calvin]

Hi,

yes the Wilson is rather over-the-top in this application. 
THD in this circuit is so low already with the simple CMs, that any improvement is rather academical.
So I prefer the 3-transistor CM, where the output leg´s CM-transistor is ´cascoded´ by a beefier transistor to cope with the heat power losses (and also still providing for higher output impedance).
The two mirroring transistors can still be small signal transistors, as their Vce is held very small and hence the power losses are small ... which allows the use of matched Duals.
Wilson requires tightly matched CM transistors,which is the case in integrated circuits.
Using say typical BC550s unmatched and the Wilson oscillates very probabely.

regards
Calvin

[magic]

THD ought to be dependent on "beta linearity" of the transistors in this circuit, so using something better than BC5x0 could be a simpler solution than Wilson, actually. There are transistors which are basically ruler-flat from sub-1mA to tens of mA, so they should be essentially ideal at the 6mA bias point.

[mawyatt]

The original circuit would likely be DC unstable in the sense that the collector currents of Q2 and Q4 must be almost exactly matched over temperature & time, and Q3 collector is supplied thru Q2 emitter, so Q2 collector current as a common base stage is created by Q3.

Seems this circuit begs for some sort of bias point stability negative feedback to remain stable over temp and time without introducing excessive waveform clipping on large output signals.

Also the output signal swing doesn't take advantage of the dual supplies (+-18V) if important in usage, as this is limited to +18 and ~ 0 volts swing before the output AC coupling, so ~ 9VPP at output.

Best,

[13hm13]

that circuit runs under the name ´Jocko´ and has its own thread in the DIYaudio forum.
As mentioned before its a common Base/Gate/Grid structure that basically functions as a impedance and level matching circuit.
It presents the DAC -which is a not an overly good current source with only a couple of hundreds of Ohms and level-varying output impedance- the required low input impedance at 0V and offers a much higher output impedance and voltage compliance.
It is well suited to current sinking DACs featuring a offset current.
Changing to a PNP topology it is well suited to current sourcing DACs like the popular PCM179x series from TI.

Calvin -- thanks for your detailed reply!
About audio DACs that are current sinking vs. current sourcing, was there ever compiled a list ?
Older dacs (before PCM179x) were "sinking"?

[13hm13]

The original circuit would likely be DC unstable in the sense that the collector currents of Q2 and Q4 must be almost exactly matched over temperature & time, and Q3 collector is supplied thru Q2 emitter, so Q2 collector current as a common base stage is created by Q3.

Seems this circuit begs for some sort of bias point stability negative feedback to remain stable over temp and time without introducing excessive waveform clipping on large output signals.

Also the output signal swing doesn't take advantage of the dual supplies (+-18V) if important in usage, as this is limited to +18 and ~ 0 volts swing before the output AC coupling, so ~ 9VPP at output.

Unclear what you mean???
The ckt (an I/V, or current-to-voltage stage for intended for "older" current-output d/a audio chips) was pretty much designed to be "plug-n-play" ***. There are variable resistors for tweaking biases and one hardly needs all 18 v. for driving a simple line-level out.

*** "Plug-n-play"  meaning one can simply pull out the OEM opamps from, say, a CD player and replace with that ckt. Not sure how it measures. But --  built EXACTLY as shown in OP -- it  subjectively/sonically  blows opmaps out of the water.

[magic]

Did you build the exact circuit you posted?
What is the collector voltage of Q2/Q4?

Because what we suspect is that you didn't, and if you did, you would have a great trouble controlling that voltage.
Even a small mismatch between steady state collector currents of Q2, Q4 is expected to make one of them saturate.

[mawyatt]

The original circuit would likely be DC unstable in the sense that the collector currents of Q2 and Q4 must be almost exactly matched over temperature & time, and Q3 collector is supplied thru Q2 emitter, so Q2 collector current as a common base stage is created by Q3.

Seems this circuit begs for some sort of bias point stability negative feedback to remain stable over temp and time without introducing excessive waveform clipping on large output signals.

Also the output signal swing doesn't take advantage of the dual supplies (+-18V) if important in usage, as this is limited to +18 and ~ 0 volts swing before the output AC coupling, so ~ 9VPP at output.

Unclear what you mean???
The ckt (an I/V, or current-to-voltage stage for intended for "older" current-output d/a audio chips) was pretty much designed to be "plug-n-play" ***. There are variable resistors for tweaking biases and one hardly needs all 18 v. for driving a simple line-level out.

*** "Plug-n-play"  meaning one can simply pull out the OEM opamps from, say, a CD player and replace with that ckt. Not sure how it measures. But --  built EXACTLY as shown in OP -- it  subjectively/sonically  blows opmaps out of the water.

As mentioned by magic above, think if you actually built this and tested you would experience the concerns about the issues with Q2, Q3 and Q4 collector currents. If you want to "see" this effect during simulation, then add a small voltage source in series with each transistor base and add a few +- 10s of millivolts randomly and monitor the collector of Q2 and Q4 output voltage. What you should see is this voltage changing significantly wrt the random changes in transistor Vbe as emulated by the additional series base voltage sources, especially Q3 and Q4. For example, a 10mv change in Vbe of Q3, or Q4 will cause a 40uA change in collector current which will cause a large change in Q2 and Q4 collector voltage. Not to mention the effects of Beta variation, Early effects, temperature and that Q3 and Q4 are different type transistors (npn vs pnp).

Please remember is is about DC bias and not AC response. Since the AC output impedance is dictated by R1 it's low, but the DC output impedance is the collector impedance of Q2 and Q4 in parallel which is very high, likely 100's of K ohms. So any collector current change causes significant collector DC voltage change, which is not good for bias stability.

Anyway, hope this helps.

Best,

[13hm13]

Did you build the exact circuit you posted?

Yes. On veroboards, three times (two separate photos taken from inside two different CD players, shown below. Both L and R channels on same Vero). I know that I use Bourns pots for some Rs', for fine tweaking.[I also shot some video, years ago, of CD player inside, with the ckt. I'll have to dig it up and post it]

Because of the delicate, physical position the boards are placed -- and have been for over 12 years; see photos -- I am not going to disturb them, moving them to probe for voltages, etc. I did that years ago and was satisfied with the results. They play music wonderfully. As can be seen, the OEM opamps were evacuated. One further note is that I am using +/- 15 v per the opamps' OEM power regs.

Also note that orig. creator of that ckt -- way back in 2002 -- posted it in ready-to-use condition. Many followed that thread on diyaudio and built the ckt as given.

CD player 1 with ckt:





CD player 2 with ckt:

[Zero999]

Q2 is the only transistor amplifying the input signal. The rest are for biasing. Q3 is a current sink on the input, Q4 is a current source for the output and Q1 shifts Q2's base above 0V, enabling it to turn on, even if the input is 0V.

[magic]

Okay, I guess it works, then.
With enough

The only interesting voltage is DC on the left side of C1 (referring to your fist schematic).
If this is too close to ground or the supply then asymmetric clipping may occur.

Other than that, the circuit is fairly simple and uncontroversial, I think.

[13hm13]

Note that I am not the orig. designer of that ckt or anything similar to it. I just built it from the provided schema, shown in OP (and again, below).

Other than that, the circuit is fairly simple and uncontroversial, I think.

I still feel the original query was not succinctly or thoroughly answered. Indeed, there may be more than one topology used in the design. Yes, common-base. And there is a  mirror in there as well. 

I'm posing the circuit as test or exam question I often encountered in my college days.

The exam question may state:

Describe and characterize the circuit below.
 [HINT: It is an audio i/v, meant to be fed by a current-output audio DAC] You may also characterize the ideal DAC that might feed this i/v. For example, look at the datasheet for the Philips TDA1541 dac IC here. Note on pg. 6 of the datasheet, the stated AOR and AOL full- and zero-scale currents:
Your answer(s) should be brief.  You can use bullet points, etc.
BONUS: Improve the circuit with as little modification as possible. E.g., add a SINGLE extra cascode transistor (state where).

[magic]

My answer was about as laconic as your question

There is no current mirror here. Q2 may superficially resemble one, but its emitter is left floating so its Vbe is not forced equal to Q1's Vbe and its current is not equal to Q1 current.

Q2 is effectively an emitter follower which forces input voltage to be near ground. It would be ground exactly (save for transistor mismatch) if Q1 and Q2 currents were equal, but Q1 current is 5x less so expected Q2 emitter voltage should be about -40mV. Q1 current is ~1.2mA, determined by R4 and rail voltage. Q2 current is simply Q3 current, or ~6mA by my calculations, plus whatever is fed into the input.

Input impedance of this circuit is the intrinsic emitter resistance of Q2, about 26mV/6mA = 4.3Ω, or maybe a little higher if Q2 gets warm. It's not perfectly constant (increases if the DAC sources current, decreases when it sinks) so perhaps some nonlinearity may occur, depending on the output resistance of the DAC (I have no idea what it might be).

At AC frequencies, Q2 collector is loaded by R1. This provides transimpedance "gain" of 2.49V per mA of DAC current.

At DC, R1 is disconnected by C1 and small mismatch between Q2 and Q4 collector DC currents will cause large shift of collector voltage. This is what we complained about.


Improvements:

I'm OCD so I would want to do something about the potential DC voltage issue. Maybe remove Q4 and simply connect R1 to the positive rail, filter the positive rail well to avoid noise injection. See the first circuit posted by Calvin.

Alternatively, a DC servo, perhaps by feeding lowpassed Q2 collector voltage back to Q3 base, but it feels like overkill compared to the above.

Maybe make Q2 a Sziklai pair to reduce input impedance of the circuit, see Calvin again. Not sure if necessary or useful.

The second example from Calvin eliminates the capacitor and makes everything DC coupled, if you are OCD about that.

[13hm13]

My answer was about as laconic as your question

Thx for your followup!
HOWEVER ....

There is no current mirror here. Q2 may superficially resemble one, but its emitter is left floating so its Vbe is not forced equal to Q1's Vbe and its current is not equal to Q1 current.

What's going on at Q1 looks like a current mirror.

See:

https://circuitdigest.com/tutorial/current-mirror-circuit
https://wiki.analog.com/university/courses/electronics/text/chapter-11

But, yes, Q2's config. does confuse things.
I'm not sure why Jocko used this i/v design for low-BW audio application? Jocko's background, IIRC, was as an RF engineer.