PLL VCO

[electrolust]

I'm following the guidance at http://mysite.du.edu/~etuttle/electron/elect12.htm to try and build a PLL circuit for very low frequencies: .5 to 4 Hz.  I'm using the LV version of a 4046.  My VCC is 3.3V.  My input will be square wave and so I would use the PCII.

Using the method in the linked article to isolate the VCO, when I get the R1 and C1 values so that the VCO produces 1Hz per volt (as a starting point, I guess this wouldn't be my final values), I find that removing the input signal causes the VCO to stop working.  With no signal, is this considered the "free running frequency"?  Note that my R1 C1 values are well, well beyond the "design spec" (I'll post a separate question about that later), in order to achieve such low frequency output.

It seems to me that using PCI, this is a problem.  But using PCII, when the signal is locked the output of the PCII is VCC/2.  At maximum lag of 180° the output of PCII is 0V for half the cycle and VCC/2 for half the cycle.  Does this average to VCC/4?  (Maybe I need to consider RMS but not the main point of my question.)  Similarly at maximum lead do I consider this an avg of 3VCC/4?

Do I only need to worry that the VCO "works" between 1/4 and 3/4 VCC?

[rs20]

Not an answer to your question, but have you considered making a PLL that operates from, say, .5 to 4 kHz and then plonk a divide-by-1024 at the end of it all? What's your input/reference frequency?

[electrolust]

Sorry if it wasn't clear.  My input frequency ranges from .5 to 4Hz.

Most of the beginner PLL sites do talk about divide by N (and the utility for creating a multiplier), so yeah I thought if it is important to operate close to 0V that I could do that.  Being a noob and not knowing what divisions are readily available I was thinking /10 but /1024 sounds really great and being in the khz range seems much closer to where the VCO wants to operate.

But as to the original question do you think I am correct in thinking the VCO will never see less than VCC/4 anyway so as long as it works it's ok?  One problem I'm facing is that I'm extremely limited on board space and the 4064 itself is quite big.  Not sure if I have enough room for another chip that size.

[Chris Mr]

Sounds intriguing!

With a 4046 it's a good idea to start thinking in terms of the usable range of the input voltage.  In the data sheet it gives the minimum and maximum input voltages to be 0.3 and 0.7vcc.  From experience, outside of that expect the unexpected.

So one usually sets up the thing with a preset potentiometer between these two levels.  Say a 10K preset occupies the voltage between 0.3 and 0.7 (if it were a 1v power supply) so 0.4v.  I = V/R so current in the 10K preset is 0.4/10000, 40uA.  To get the two resistors at 0.3v we do R=V/I so 0.3/40uA gives 7.5K.  So you have a 7.5K resistor (from any supply voltage) to one end of the 10K preset, then another 7.5K resistor (if you're feeling cautious use 8K2) from the other end of the preset to ground; wiper of the preset goes to the VCO input (no phase detector connected yet).

When you adjust the preset those are the viable input voltages.  Now you can measure the frequency at the output when twiddling the preset.  You can also just use a changeover switch (instead of a preset) to go from one end to the other.

You can also put preset resistors from the two pins (R1 and R2) to ground and twiddle them to get what you are after.

Now, with this setup you can apply your input signal to one PC input, other PC input to VCO output, and watch the PCII output (on a scope) as you twiddle the VCO voltage.  This is a great way of getting confidence in what you are doing as high VCO voltage gives PCII output low and vice versa (else the PC inputs are the wrong way round).

These are pretty low frequencies so, as already mentioned, you might want to divide down first.

As a rough guide, with PLLs, expect it to take about 10 input cycles to lock when you get the loop time constants right - so at 0.5Hz about 5 seconds.

Hope that helps

[electrolust]

That helps a lot, thanks.

So I did discover that even when operating in the preferred VCO frequency range (as determined by the min/max R1 R2 C1 ranges given in the datasheet), removing the input signal causes the VCO to flip out.  So I guess from that and from your response, I am confident that I do not need to be concerned outside of 0.3vcc <-> 0.7vcc.

So I have another question.

I found a set of R1 C1 values (R2 absent) that generate 2.00Hz @ vcc/2 (1.65v).  I didn't check the frequency at 0.7vcc, I won't be able to check until tomorrow or possibly Monday.  However, assuming that the center frequency is ok and the range is ok, the problem is that my R1 C1 values are well outside of the "required range".  What problems would I expect to encounter running it outside of this range?  Just linearity problems or would I have reliability problems?

I question whether it's necessary to stay within the prescribed values because even the graphs on the datasheet provide curves for values very far outside of the apparent design limits.  For example, here are the upper limits for R1 per TI datasheets:

CD4046B: 5k
CD74HC4046A: 300k
SN74LV4046A: 50k

Yet the graphs provided go well into Mohm range for R1.

[electrolust]

As a rough guide, with PLLs, expect it to take about 10 input cycles to lock when you get the loop time constants right - so at 0.5Hz about 5 seconds.

Thanks for that guidance.  With the loop filter I have currently, lock does take quite awhile but when it locks it is dead on stable.  That was quite fun to watch on the scope.  5s is too long for sure though.  I was going to keep playing with the loop filter under the impression that I can gain lock faster but I guess it has to go through at least a few cycles.  I guess the prescalar/divider won't help.  Instead of a divider on the VCO output, could I multiply the input signal x1024?  I suppose a PLL-based multiplier wouldn't work for this case ...

[danadak]

The problem with high values of R are the offset it creates due to MOSFET
gate leakage and input protection diode leakage. Aggravated by high T I
might add. Look at leakage spec of part, and that x R will give you the V
offset that produces.


Regards, Dana.

[rs20]

Another thing; if you want to get an actual analog loop PLL running at ~1 Hz just for fun, by all means, go for it. But it seems to me that you could achieve the same goal with much more ease, precision and faster "lock" time* by using a microcontroller than measures the incoming pulses (using a timer capture pin) and configures a PWM accordingly. You could easily dial in however much jitter cleanup and other bonus features you wanted too. Easily within the capabilities of virtually any 8-pin PIC or AVR.

* By faster lock time, I mean, it sees two input pulses and immediately attains a practically perfect lock (assuming no jitter in the input).

[Chris Mr]

It might help, for you to get other ideas, if you describe what you are attempting.  As previously mentioned, there are lots of other ways to do these sorts of things.  I was working on the idea that you were interested in PLLs, hence the answer about input voltage etc.  It is very slow, your input signal, so there are bound to be other ways.

[radar_macgyver]

GPSDO designs use microprocessors to implement the loop. Various hacks are available to improve the lock times. Also, you don't have to worry about dielectric leakage from the large capacitors needed for an analog loop operating at such low frequencies.

[T3sl4co1l]

If you need an arbitrarily fast lock, consider a FLL (frequency LL) instead of PLL.  Or combine them, so the FLL works until the PLL locks.  No matter how you tweak the filter values, you can't get a PLL to lock faster than such-and-such, for a given capture range of this-or-that.

Or if your input is well defined after all, consider not using a PLL in the first place!

When the input is open circuit, it's receiving noise (notice the input stage has extra buffers, analog bias, and recommends AC coupling -- at least, I recall this is typical; there are many variants of '046 and you didn't mention exactly which one you're using).  Would you not expect the VCO to "flip out" under this condition..? 

Tim

[rgarnett1923]

Hi,

I had a similar need for a low frequency PLL.  I did it in software using C code do the phase comparitor, a PI controller for the loop filter to one of the on-board counters  to produce the output.  I used an STM32 low power processor that synthesized a 1 Hz signal from a 1.1 Hz signal using one PLL and then synchronised this with a 1 Hz signal from a GPS with a 1 PPS signal.

Dead easy and if you use a 32 bit timer clocked by an auxiliary timer you can get excellent resolution, virtually an analog oscillator.

RJG