EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: miker7940 on April 01, 2016, 05:32:40 am
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Okay, some of you may have seen my previous thread regarding reverse engineering a Chip on board.
I've decided that way is just going to be too hard.
I've heard some people have recreated this in CPLD but I know nothing about that and it seems no one is sharing how to do it.
The chip in question is a MBC5 chip by Nintendo, as a memory bank controller for their game cartridges. I'm trying to make a homebrew game cartridge.
I understand how to make the rest of the cartridge, but I have to use a MBC5 chip from a existing cartridge.
So, I'm wondering if anyone thinks it is possible to write a implementation of the MBC5 memory bank controller in AVR-C?
There is a lot of information on the MBC5 on the internet, so getting the information shouldn't be a problem.
Thanks everyone for your replies.
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If I had to guess, I'd say no. Memory controllers usually need pretty speedy latency, and with a CPU in the way you basically have to give that up. You could perhaps implement it with logic gate ICs and a micro together, but you might as well just use a CPLD then anyway. If I recall, this chip does something like remapping a chunk of the address space to another ROM (or another section of the sample ROM) and then funnels the R/Ws to the right place, in which case I'd almost certainly say no. But I'm happy to be proven wrong ^-^
A CPLD is a bunch of gates you can reconfigure on a chip. If one had an understanding of the exact process undertaken by a memory controller, it would be no more difficult to implement it on a CPLD than with just logic gates (in fact, it would probably be easier with the CPLD).
A way to explore a little more about this might be to look at schematics for old arcade boards to see how they handled switching between ROM chips.
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If I had to guess, I'd say no. Memory controllers usually need pretty speedy latency, and with a CPU in the way you basically have to give that up. You could perhaps implement it with logic gate ICs and a micro together, but you might as well just use a CPLD then anyway. If I recall, this chip does something like remapping a chunk of the address space to another ROM (or another section of the sample ROM) and then funnels the R/Ws to the right place, in which case I'd almost certainly say no. But I'm happy to be proven wrong ^-^
A CPLD is a bunch of gates you can reconfigure on a chip. If one had an understanding of the exact process undertaken by a memory controller, it would be no more difficult to implement it on a CPLD than with just logic gates (in fact, it would probably be easier with the CPLD).
A way to explore a little more about this might be to look at schematics for old arcade boards to see how they handled switching between ROM chips.
Thanks very much for your reply - I've seen earlier versions of the MBC chip created with just logic gates, but I found a way to make the MBC5 chip using a xc9536 CPLD chip - Wish me luck :)
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There are recreations of the MBC5 on FPGAs already, hobbyists have been doing them for years. The operation should be described in pandocs. Any Gameboy emulator will have an implementation too, look at the source code.
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http://gbdev.gg8.se/wiki/articles/MBC5 (http://gbdev.gg8.se/wiki/articles/MBC5)
Looks like a pretty simple address decoder, two registers one for RAM bank and one for ROM bank.
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http://gbdev.gg8.se/wiki/articles/MBC5 (http://gbdev.gg8.se/wiki/articles/MBC5)
Looks like a pretty simple address decoder, two registers one for RAM bank and one for ROM bank.
All Gameboy MBCs are roughly that simple, the only exception is the MBC3 adds a RTC
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Thanks everyone for your replies - atm I am working on making it work in CPLD.
If anyone has any more simpler solutions, I would be more than happy to hear them!
Thanks!