Preventing toggling GPIO output on MPU boot

[davegravy]

Hi everyone,

I’m working on a project where I have an MPU connected to a device via an nMOSFET in an open-drain configuration. At power-on, before the OS loads and configures the GPIO, the MPU output is held HIGH (1.8V), which undesirably powers on the controlled device.

I’m looking for best practices to handle this situation. Here are the solutions I’ve considered:

1. External Pull-Down Resistor: Adding an external pull-down resistor on the output that’s significantly lower in resistance than the default internal pull-up of the MPU at power-on. According to the datasheet, the MPU’s internal pull-up is at least 100kΩ, so I could use a 10kΩ resistor, which would yield less than 0.164V at power-on (below the nMOSFET threshold)

2. Extra nMOSFET: Using an additional nMOSFET to invert the signal logic.

My priorities are robustness and low power consumption. The pull-down resistor would only add about 324µW, which is negligible compared to the MPU’s power consumption.

Are there any reasons to choose one solution over the other, or is there a better option I haven’t considered?

Thanks for your insights!

EDIT: I'm also constrained on GPIO count

[oPossum]

74AHC1G86 or similar connected to two GPIO.

[davegravy]

74AHC1G86 or similar connected to two GPIO.

I think I understand how this would work, I didn't mention I am a bit tight on GPIO count but if there's a compelling reason this is preferred over option 1 or 2 I mentioned I'd consider it.

[pcprogrammer]

Best to add some more information here. Which MPU are you using and which GPIO of that MPU. How is the mosfet connected to the MPU, etc.

Normally GPIO pins are set as input on reset and can be seen as high impedance and in a startup sequence it is possible to set the output high or low before enabling it as an output.

When it is indeed an input on and after reset a pull down resistor can do the trick. But it is a blind guess without more information.

[Peabody]

I’m working on a project where I have an MPU connected to a device via an nMOSFET in an open-drain configuration. At power-on, before the OS loads and configures the GPIO, the MPU output is held HIGH (1.8V), which undesirably powers on the controlled device.

Really?  And it's your sense that this is the GPIO in input-pullup mode rather than an active high output?  What processor is that?

1. External Pull-Down Resistor: Adding an external pull-down resistor on the output that’s significantly lower in resistance than the default internal pull-up of the MPU at power-on. According to the datasheet, the MPU’s internal pull-up is at least 100kΩ, so I could use a 10kΩ resistor, which would yield less than 0.164V at power-on (below the nMOSFET threshold)

Aren't you supposed to have a pulldown resistor on the gate anyway, to prevent it from ever floating?  Have you tested what value resistor would prevent the mosfet from turning on at powerup?

Depending on what and how often the mosfet is switching, and how long the spike lasts, a small R/C on the gate might work without any cost in power.

Edit:  Nevermind.  I just read your other thread, and realized I have no idea what this is all about.

[davegravy]

Best to add some more information here. Which MPU are you using and which GPIO of that MPU. How is the mosfet connected to the MPU, etc.

It's microchip AT-SAMA5D27, the SBC is KSTR-SAMA5D27

The GPIO is PC25

[davegravy]

I’m working on a project where I have an MPU connected to a device via an nMOSFET in an open-drain configuration. At power-on, before the OS loads and configures the GPIO, the MPU output is held HIGH (1.8V), which undesirably powers on the controlled device.

Really?  And it's your sense that this is the GPIO in input-pullup mode rather than an active high output?   

Not sure.

Aren't you supposed to have a pulldown resistor on the gate anyway, to prevent it from ever floating? 

Am I? This is why I'm posting in the begginer forum  That makes sense though.

Depending on what and how often the mosfet is switching, and how long the spike lasts, a small R/C on the gate might work without any cost in power.

It's switching the PWR_on pin of a cellular module. I need to pulse the PWR_on pin low with a pulse width of a few seconds, so very low switching frequency.

[pcprogrammer]

The IO setup of this MPU is rather complex and a quick scan of the section of the manual about the PIO did not directly show the reset state of the actual pins, but as there is the need for the clock to the PIO peripherals to be enabled for output functionality, I think it is safe to state that the IO pins will be inputs on power up and after reset.

To avoid the mosfet turning on on power up a pull down resistor should do the job. Do make sure that the mosfet you choose for the job works with the 1.8V output level you mentioned. The SBC you are using seems to allow selection between 3.3V and 1.8V IO levels, so is there a reason not to use 3.3V?

[Doctorandus_P]

Most microcontrollers have their I/O pins floating during the reset state. I am a bit surprised your's has internal pullups enabled. Maybe your uC only has this on some of it's pins. If so, can you move your pin to another location?

And external pullups / pull downs are common. I once had data corruption on an RS485 network when pluggin in new modules on a live cable. I fixed that by using a pull down resistor on the output enable pin of the RS485 driver.

And as others have written, you should not let the gate of your mosfet floating. Especially with power MOSfets, this can lead to a situation where the gate is partially opened, and can easily cause overheating and destruction of the FET.

And if you can pull the I/O pin down with a 10k resistor, then it definitely is not an active high output. Active high outputs generally can source some 10 to 40mA.

[davegravy]

The IO setup of this MPU is rather complex and a quick scan of the section of the manual about the PIO did not directly show the reset state of the actual pins, but as there is the need for the clock to the PIO peripherals to be enabled for output functionality, I think it is safe to state that the IO pins will be inputs on power up and after reset.

To avoid the mosfet turning on on power up a pull down resistor should do the job. Do make sure that the mosfet you choose for the job works with the 1.8V output level you mentioned. The SBC you are using seems to allow selection between 3.3V and 1.8V IO levels, so is there a reason not to use 3.3V?

I've just been inspecting the PINCTRL register right after boot and it is indeed an input with a pullup.

I'm using RUM001L02T2CL with V_gsth from 0.3 to 1.0V.

I chose 1.8V for a couple reasons. 1) the LTE module I'm communicating with uses 1.8V signaling and I'd hoped to avoid a level translator (ultimately I added one anyways to isolate the LTE IO pins) 2) to minimize power draw as this is an unattended solar-powered IoT project. I'm not sure I'm realizing a significant savings next to the MPU draw but in the future I'm hoping to be able to deep sleep the MPU so it might become significant.

[radiolistener]

Probably your MCU GPIO pin is damaged, because it should be configured as high impedance input after reset and should not affect the level on connected line.

Such damage can happens if you put too much voltage on the GPIO pin. It's internal protection diode may be damaged and make short circuit on the MCU VCC line. Sometimes it is partially damaged and can continue works, but has significant current leakage when configured to input mode.