Author Topic: Propagation delay short?  (Read 1109 times)

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Offline zappedy

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Propagation delay short?
« on: June 07, 2015, 12:36:18 pm »
I want to read a 16 bit value over an 8 bit bus, so I'm using 2x 374 latches, and alternating which one has output enabled.

If I select from only a clock signal + the same clock signal but inverted through a not gate, there will be a short interval, about one propagation delay long, where both latches are driving the bus.

Is there any risk that having both latches drive the bus simultaneously could fry something? Do I have to make sure only one output is enabled at any time?

(It works in the simulator but I haven't wired it up yet because I'm going to have to order a PCB because the circuit grew large. I think the simulator I use, Logisim, mostly ignores analog details of circuits. I can't wrap my head around the different Spices unfortunately)
« Last Edit: June 07, 2015, 01:00:29 pm by zappedy »
 

Offline dom0

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Re: Propagation delay short?
« Reply #1 on: June 07, 2015, 01:17:23 pm »
If I select from only a clock signal + the same clock signal but inverted through a not gate, there will be a short interval, about one propagation delay long, where both latches are driving the bus.

You forget the propagation delay from output en/disable to the outputs of the latches. These are longer than the tpd of a inverter and are usually asymmetric by a couple ns (enabling outputs takes longer than disabling them).
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Online Ian.M

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Re: Propagation delay short?
« Reply #2 on: June 07, 2015, 01:22:35 pm »
Not good.  You really want non-overlapping enable signals.

The '374 OE pin is active low, so your best bet is to OR a delayed version of the enable signal with the original signal to add some deadtime at the leading edge of the low going pulse.   Getting complimentary enable signals from a single squarewave is best done with two XOR gates so you can match the propagation delays.
 


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