Power trace size of GND decoupling

[JonPyro]

Hi all,

I am designing a board using the tb67s249ftg stepper motor driver chip. It has two sets of power pins for the motor driver power supply. I was wondering about trace sizes for the ground pad of the capacitor decoupling across those pins. In theory the chip could be drawing a couple of amps so the positive trace needs to be quite wide, however, how wide should the trace be connecting the ground pad of the decoupling capacitor to ground plane be? Surely all the current is flowing into the chipset and little to no current flowing though the capacitor (open to debate I know), so only a thin trace, say 5mil should be ok on the GND side? I was wondering whether there are any rules of thumb?

If this was just a standard logic chip I would normal make all my power and GND traces the same size, usually about 0.25mm as I generally work with low currents and not really worried about being precise. However, this has made me think a little bit more about my general lack of understanding of PCB design.

Thanks for any help

[Zero999]

I'd say as thick and as short as possible. The capacitor trace will carry a significant dynamic current, as its purpose is to absorb the peaks and ride out the troughs in the supply voltage, as the stepper motor driver is switching. It isn't just the resistance which needs to be kept as small as possible but also the inductance and keeping the track wide and short will help.

[james_s]

Ideally I'd put a ground plane under the whole board that is as unbroken as possible and stitch the ground pin do that with several vias. Put the decoupling capacitor as close as possible to the Vcc pin and stitch the other side of that capacitor to the ground plane. Is this really necessary? Probably not, but you do have to be careful, I had a lot of difficulties when I first started designing PCBs until I figured out the importance of proper grounding technique.

Read the datasheet carefully, often they will give you important hints on PCB layout.

[T3sl4co1l]

Local bypass capacitors don't carry much RMS current. Don't worry about it.  Once the nets are routed a bit away from the chip and you have the space, go up to trace widths that are adequate for the DC capacity.

Worry more about width and length for stray inductance.  That's what, 0.5mm pitch QFN?  10 mil traces can connect to those, and 0402 caps fit right inbetween (broadside).  Or 0603 lengthwise with somewhat finer traces.

Can use the exposed pad for ground connections.  It needs thermal vias anyway.  Pour solid ground on bottom for 2 layer build, or preferably mid ground on 4 layer.

Tim

[JonPyro]

Thank you all for your words of wisdom. I think I will need to adapt my board stack up as well now.

[OwO]

Why would you even think of using a 0.12mm trace for a power connection? I use minimum 0.3mm width when connecting to pads (depending on size) because thinner traces rip off more easily for zero benefit. Use thin traces only if you have to. I hate seeing "modern" board designs with almost no effort in layout, using thinnest supported traces everywhere, absolute minimum clearance everywhere even when there is plenty of space (a telltale sign of push-and-shove routing), and lots of blank space not filled with copper (waste of etchant).

[JonPyro]

That was my question really. If most people judge track size by current carrying capacity, then how much current does the ground pad of a decoupling capacitor actually carry?

[T3sl4co1l]

For signal purposes, perhaps fractional mA, perhaps uA.  For power purposes, A easily.

I once made a converter with seriously constrained dimensions.  I could only fit two bypass caps, one input, one output:



Ćuk topology, so the input and output ripple aren't even all that bad.  It's still a matter of scale, and the 5A RMS or so still has to go somewhere.  After successful operation on intermittent loads, one day I must've loaded it a little heavier or longer, and the heatshrinked capacitor lead fused open: https://www.seventransistorlabs.com/Images/CukHack4.jpg

I rebuilt it in a slightly larger enclosure, able to fit four such caps, plus some ceramics.  Much quieter now, plus it doesn't cook off under rated load.   https://www.seventransistorlabs.com/Images/CukHack5.jpg

Tim

[iMo]

Here is an LTSpice model of a PCB trace with resistance and TC - the dotted line in the schematics is the Trace, with a length and width (in mm) you may define, by default 35um thick copper.
You may see what it does in real circuit.
You may add a trace inductance in series with the resistance as well.

PS: on the left you may see a 100mm x 0.256mm PCB trace creating 190mV drop with 1A current (at T=27C, not counting resistance change caused by temperature while warming up, but it could be added to the model too).