Pull up on the output of an LS series IC

[MrAl]

I don't understand that obsession with 3.5 V and simulation. Just looking at the totem-pole circuit it's can be seen that when the output is logic high, it's effectively open circuit because current can't flow out of the top transistor, so the pull up makes transistor base rise to the 5V rail. The 3.5 V (3.6, 3.7 whatever) would happen if there were a load to ground due to the 2 diode drops. But there isn't a path to ground because the lower transistor is off.

If the transistor load is something like a bulb then turn-off time doesn't matter. Then if the transistor is perfect you don't need a pull-up. But in case you encounter a slightly leaky cb junction, the pull-up ensures that the transistor will never be partly on.

Hi,

The 'obsession' is due to the fact that we would like to see spice models work as close as possible to the real life parts they model.  If they dont, it becomes a concern and thus a new model can be made to better mimic the behavior of the real life part.  It's not as much to do with this particular circuit as it is with future circuits where we would like to be able to model the significant behaviors as well as possible.

[MrAl]

Yes that's interesting because the raw transistor model would do that too.
But i suspect that the design point should be more like 3.5 volts, as that is what they specify.  I dont know the reason for that though, but i do know that in the raw transistor model it would take a resistor around 500 Ohms to get the output to go to 3.4 volts or there about.

I don't understand what you're referring to.  Do what too?  500 ohms placed where?  3.4V under what conditions?  Who specifies 3.5V for what?  The original schematic in post #1 has Vcc at 5V, which is what you would need for 74LS.   Are we talking about two different circuits?
 

So it is unclear why the spice model is not showing what you are measuring but it does show what the data sheet specifies.

Could you be more specific?  Which measurement are you referring to?  What does the spice model say?

Hi,

Yeah sure.

First, if the spice model shows a 3.5v output (approximately) even with a 1k pullup when the output is high and you or i measure 4.9v with a 1k pullup then there is something missing about the spice model and that says that it cant be used for any circuit that is atypical of a regular logic circuit.

Second, if we model the device with discrete spice NPN transistors, we see a behavior more typical of what you or i would measure in real life, and in order to meet the specs of the data sheet or the full spice model we would for example have to connect a 520 Ohm resistor from the output of the gate to ground.  That resistor would draw enough current to mimic the behavior of the original spice models.  It's only to show that it seems a bit ironic that when we use the internal transistor diagram we dont get the data sheet behavior unless we sink some current to ground, and it would be somewhat significant for an LS type gate output.

So the first point is more important, the second is just a comparative analysis of what we should have an what it takes to match the data sheet and spice models.
The catch though is that these gates were made for connecting to other gates, which means they would be subject to the constraints that the input impedance of the next gate would present.  Strange though, using the discrete transistor model shows near zero current to ground with a high logic level input.

So the conclusion is that the spice model is lacking.

The next test we would have to do is check the fall time of the output when the output is pulled up by perhaps 4.7k.  Since the fall of the output would have to go through a larger transition from H to L it will take a little longer to get to 0.5v which would be enough for the next gate.  How much we can probably estimate based on the current fall time.  This doesnt seem to be a big concern with this particular circuit however.  It would only possibly matter in future designs we wanted to test mathematically or in a spice environment.

[Peabody]

Could you please post the spice schematics your comments are based on?  It doesn't sound like you are modeling the same circuit as the one I breadboarded, which didn't have a 1K pullup at all.

[retiredfeline]

It's a worry when you pluck a figure like 3.5 V from the datasheet and treat as an operating point. When the breadboarded circuit behaves just like you can predict from the schematic of the totem pole circuit and not the Spice model then you have to ask yourself if the model or the initial conditions are correct for the situation.

3.5 - 3.7 V isn't some kind of value the LS output "tries to maintain". In the presence of no path to ground and a path from 5 V via the transistor and base resistors, it will go higher as the practical test by Peabody shows. Entirely predictable, without the benefit of simulation.

And there is nothing wrong with using a gate T-P output this way to drive a transistor. You just have to operate below the sinking capacity of the gate (10 LS unit loads). But open collector outputs are still needed when the high side is greater than 5V or greater current sinking is needed.

[MrAl]

Could you please post the spice schematics your comments are based on?  It doesn't sound like you are modeling the same circuit as the one I breadboarded, which didn't have a 1K pullup at all.

Hi again,

That's the first thing i checked and was disappointed that there was no schematic just some commands like
you would use for a diode, and some timing.
Here's the entire thing and notice that it says 7402 not 74LS02 but it was picked from their listing for 74LS02:

.SUBCKT 7402  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0

U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_02 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.model DLY_02 ugate (tplhTY=12ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)

.ENDS  7402

Maybe we can get a better model.


Here's another but it's almost the same thing:

*  Quad 2-Input Nor Gates
*
*  The TTL Logic Data Book, 1988, TI Pages 2-13 to 2-17
*  bss    2/3/94
*
.SUBCKT 74LS02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0

U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS02 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.model DLY_LS02 ugate (tplhTY=10ns tplhMX=15ns tphlTY=10ns tphlMX=15ns)

.ENDS  74LS02

[Peabody]

Sorry, but I'm not able to follow what you're doing.  So I'm going to bow out of the conversation, and hope that the OP has found an answer to his question.

[fabiodl]

I breadboarded this part of the circuit using a 74LS32, 1K and 4.7K resistors,  a 2N3906, and a 100R collector resistor as the load.  Here's what I got:

Code: [Select]


LS Output State          High            Low

1K and 4.7K
-----------

Vcc                     5.11V           5.10V

LS out voltage          5.11V           228mV

Base voltage            5.11V           4.17V

Collector voltage          0V           4.74V

Collector current          0mA          48.9mA


1K only
-------

Vcc                     5.11V           5.10V

LS out voltage          4.59V           227mV

Base voltage            4.59V           4.16V

Collector voltage          0V           4.80V

Collector current          0mA          49.1mA


The LS32 had a date code of 8016, so barely broken in.  Anyway, this shows you have to have base current to get collector current.  And when the LS output is high, it can't sink any current, and the transistor will stay off - with or without the 4.7K pullup.

I'd say this is a pretty clear answer, thanks!

[MrAl]

Sorry, but I'm not able to follow what you're doing.  So I'm going to bow out of the conversation, and hope that the OP has found an answer to his question.

Hi,

Ha ha, i dont blame you.  The only thing i was trying to do is establish that the models do not match the measured data, nothing difficult about that.  Neither the spice models nor the internal diagrams match anything we measure.
The actual models are internal to spice also so we cant see them.  We could try to find them on the web i guess but it's really not needed here i think.

It's more of a general area of interest for example see here:
https://electronics.stackexchange.com/questions/518248/ltspice-how-to-simulate-real-ttl-gates

So it's a known issue.
In the past i had data books that talked about using CMOS gates in analog applications.

[tggzzz]

I'm not a fan of stack space. In discourages deep understanding of fundamentals, preferring to concentrate on  superficial trivia such as which squirdle to you fettle to turn the drowpty green in WizzBang v3.87.

One example of that is in the article referenced, which contains "If you build a mixed analog digital circuit then you need to have models of real TTL or CMOS gates which have realistic current characteristics, sensing thresholds, etc.".

That's just wrong.

What you need to have is an understanding of the specification of what is and isn't guaranteed. Then you use that to design (not simulate) circuits that are insensitive to what isn't guaranteed.

All simulations are erroneous, but in some limited circumstance some are useful. Only understanding can help delineate those circumstances.

In the context of LSTTL logic output voltages, any output above 2V is a valid logic 1 level, and below 0.8V is a logic 0 level. Some outputs can and do legitimately have regular "AC noise" superimposed on a constant voltage level. Circuits have to be insensitive to that.

The pictures below show an unloaded LSTTL output, 1V/div vertically, 0.5µs/div and 5µs/div horizontally.

The logic 0 level is pretty clean (unless there's groundbounce) it usually is since it is the totem pole output's V_cesat.
The logic 1 level always well exceeds 2V by a surprisingly large amount. During +ve transition it gets to 2.2V fast, then takes 1µs ambling up to >4V. Nobody would have any cause for complaint about the 0.6V_p-p "noise on the output".

[MrAl]

Hello,

Superficial trivia?
You serious?
I dont think so.  Some data books made by the manufacturers themselves contain information like this.  That came about because they found out that designers were using digital parts like gates in analog applications like oscillators and even straight up amplifiers yet there were no specs for these parts that could relate to those kinds of applications.
You seem to be the only one spewing superficial trivia i suggest you stop.

[tggzzz]

Hello,

Superficial trivia?
You serious?
I dont think so.  Some data books made by the manufacturers themselves contain information like this.  That came about because they found out that designers were using digital parts like gates in analog applications like oscillators and even straight up amplifiers yet there were no specs for these parts that could relate to those kinds of applications.
You seem to be the only one spewing superficial trivia i suggest you stop.

I presume the context of you comment is my post. Your response is unnecessarily vituperative, and indicates you didn't read/understand what I wrote. The "superficial nonsense" refers to posts on stackspace in general, and is a consequence of the site design, moderation, and users. I stand by that statement.

I gave specific reasons for my objecting to a statement in a post on stackexchange. You have ignored the reasons and invented an irrelevant strawman argument.

Isn't it obvious that if something is specified in the data sheet by the manufacturer then you can rely on it. If not, then you can't. Simulation (as proposed in this thread) based on unknowns gets you precisely nowhere. The only option is to characterise a manufacturer's device, and hope the next instance behaves similarly. You have to repeat that with different manufacturers and hope the manufacturer doesn't change the fabrication process.

BTW, I am quite familiar with using logic gates in analogue circuits. I first time was in 1979, to build a bandpass filter with a Q of ~4000 using 10% capacitors. I used the principles I found in a 1957 paper from Bell Labs. There is, by design, absolutely no way stackexchange could be useful for that kind of discovery.

[MrAl]

Ok no problem.

I suggested that one post just as an illustration, one other person looking for info on using logic devices for analog circuits.

I see you were active in the past as was I.  It was really nice in those days with the bigger parts and wider spaced leads.

[tggzzz]

I see you were active in the past as was I.  It was really nice in those days with the bigger parts and wider spaced leads.

Probing can indeed be a pain, but I now prefer making things with SMD components - smaller, lower inductance, no holes, sane pinouts unlike standard TTL and pinout compatible derivatives.

But not BGAs, though!

[David Hess]

If the transistor load is something like a bulb then turn-off time doesn't matter. Then if the transistor is perfect you don't need a pull-up. But in case you encounter a slightly leaky cb junction, the pull-up ensures that the transistor will never be partly on.

With low power schottky logic, those are not just transistors; they have schottky diode Baker clamps which will contribute more leakage than the transistors.

One might get away without the pull-up resistor to shut off the discrete common-emitter high side PNP, but it is not something I would rely on if the application requires the PNP to be truly off.

[MrAl]

I see you were active in the past as was I.  It was really nice in those days with the bigger parts and wider spaced leads.

Probing can indeed be a pain, but I now prefer making things with SMD components - smaller, lower inductance, no holes, sane pinouts unlike standard TTL and pinout compatible derivatives.

But not BGAs, though!

Oh yes the larger SMD components arent too bad and yes no holes that's really nice.
But dont say "BGAs" around me that's a four letter curse word (ha ha).

[MrAl]

If the transistor load is something like a bulb then turn-off time doesn't matter. Then if the transistor is perfect you don't need a pull-up. But in case you encounter a slightly leaky cb junction, the pull-up ensures that the transistor will never be partly on.

With low power schottky logic, those are not just transistors; they have schottky diode Baker clamps which will contribute more leakage than the transistors.

One might get away without the pull-up resistor to shut off the discrete common-emitter high side PNP, but it is not something I would rely on if the application requires the PNP to be truly off.

Hi,

I have to agree with that id be afraid not to use at least some value pullup just to make sure.  Apparently the designer of that circuit felt the same way.

[Peabody]

If the transistor load is something like a bulb then turn-off time doesn't matter. Then if the transistor is perfect you don't need a pull-up. But in case you encounter a slightly leaky cb junction, the pull-up ensures that the transistor will never be partly on.

With low power schottky logic, those are not just transistors; they have schottky diode Baker clamps which will contribute more leakage than the transistors.

One might get away without the pull-up resistor to shut off the discrete common-emitter high side PNP, but it is not something I would rely on if the application requires the PNP to be truly off.

It seems that any leakage in the transistors or Baker clamps would simply increase the voltage at the output, which would turn the PNP even further off.  There has to be current leaking to ground to partially turn on the transistor.  But your credentials are much better than mine (I don't have any), so I'm sure you must be right.  And I have to admit that I occasionally see pullup and pulldown resistors on bipolar bases in other circuits.  But I've never used them, with no regrets so far.

How would you go about calculating the value of the pullup in this case?  Is 4.7K the right value?  How do you know?  Would 1Meg work?

[David Hess]

How would you go about calculating the value of the pullup in this case?  Is 4.7K the right value?  How do you know?  Would 1Meg work?

The nominal recommended pull-up value for LSTTL with one load is 18 kilohms.  (1) For standard TTL it is 4 kilohms.

The pull-up just needs to cancel any leakage so it could be much larger, but I would probably make it 10 times the recommended value, so 180 kilohms.  If turn-off speed is important, then it should be much lower in value.

(1) Page 5-5 of the Texas Instruments TTL Data Book.