Pull-up resistor value vs. voltage

[eddie1]

For pulling up an external (i.e. not on the same PCB) open drain signal, a resistor value of 10k seems to be the most common "general purpose" recommendation. (I know there are special situations like I2C or noisy environments that justify deviating from that.) As I understand, this is usually considered to be a good balance between noise immunity and current draw. The voltage usually isn't explicitly specified in the context of this recommendation, but can be assumed to be 5V or maybe 3.3V. I'll assume 5V for this post.

10k @ 5V = 500uA current draw, 0.0025W.

If the voltage is dropped to 1.8V but the resistor value is kept the same, current draw drops to 180uA, and wattage to 0.000324W. This, I assume, comes at the cost of noise immunity: the 10k @ 1.8V pull-up would be weaker (more susceptible to random outside noise causing the input to bounce around) than 10k @ 5V. Is this correct?

If that's correct, what would be the proper way to scale the 10k @ 5V number? Would it be:

3.6k @ 1.8V = same 500uA current draw, but 0.0009W (lower wattage)
1.3k @ 1.8V = about 1384uA current draw, but about the same 0.0025W wattage
or something else?

(The real reason this came up was an idea I had to pull up to 12V instead of 1.8V and level shift that down to 1.8V, which would let me replace a switching regulator -- currently powering an MCU and pull-ups -- with a linear regulator that only powers the MCU, without really impacting total power consumption. But first I want to make sure I understand this correctly. Which I probably don't. )

Thanks!

[David Hess]

The impedance is the same so the absolute effect from external sources is the same.  The only thing which changed is the noise immunity so to preserve the same noise immunity, the value is decreased.

Usually pull-up resistor values are determined by other factors like impedance matching, maximum current, and speed.  A given logic family will have a specific pull-up resistor value recommended.

[eddie1]

Thanks!

This is for fan monitoring. There isn't any manufacturer-recommended pull-up value. There is an old Intel document that is probably the closest thing to authoritative on the subject, but it doesn't recommend a pull-up value, just specifies maximum current (IIRC) and maximum pull-up voltage (13.2V, so 12V with tolerance).

To see if I understand all of this correctly: (I'm enclosing all of this in a quote tag because I don't want someone to come across this via Google, skim the page, and think I'm actually declaring this to be correct. It's my best current understanding of all this, but may be, and probably is, wrong in some way.)

The impedance is what matters as far as how likely the line is to pick up external noise, and that's the same at 10k @ 1.8V as it is at 10k @ 5V. But the overall noise immunity will be different at 10k @ 1.8V compared to 10k @ 5V because there is less margin in the logic threshold ranges. To quantify this, I'll use a PIC data sheet I have here: at 5V, logic low is 0-1V and logic high is 4V-5V; at 2.0V (using this because they don't specify Schmitt trigger numbers below 2.0V), logic low is 0-0.4V and logic high is 1.6-2.0V. (And anything in between those is basically undefined, I assume, which is why floating inputs are such a bad thing.)

Since this is a pull-up, external noise should (at least under normal circumstances) should only have an effect when the OD output is "high" (which means the line is actually hi-Z and the voltage is being provided through the pull-up). When the OD output is low, the line is directly connected to ground and should be fairly immune to external noise causing a voltage spike that registers an erroneous logic high. An erroneous logic high could only occur in some kind of odd, extreme situation where external noise is high enough to exceed the outputting IC's ability to sink current.

Since the absolute effect from external sources is the same at 10k @ 5V as it is at 10k @ 1.8V, you would see the same voltage drop from external noise in a given environment. But since you have less margin at the lower voltage, a (say) 0.5V voltage drop from external noise may be tolerable at 5V but not at 1.8V.

(Example that may be clearer: Let's say in a hypothetical noisy environment, a line with a 10k @ 5V pull-up, when hi-Z, will show on an oscilloscope as moving between 4.5V and 5V (anywhere in between). The same line with a 10k @ 1.8V pull-up will show as moving between 1.3V and 1.8V. That noise is tolerable on the 5V line because the logic high range provides 1V of margin, but not on the 1.8V line, so the 1.8V line would need a lower value pull-up to reduce the voltage drop and operate properly in the same environment.)

And I suppose the same external noise could also cause voltage spikes higher than the logic level, which may necessitate additional protection measures in some cases. Such spikes, however, shouldn't cause an erroneous digital input, as long as the peak voltage level isn't high enough to blow the MCU or whatever part the line is connected to.

If all of that is correct, I think I have a way to simplify this circuit a bit (on the 12V-to-1.8V part) and reduce power consumption: pull up directly to the 12V supply (since the OD output permits that) and level shift that to 1.8V for the MCU (probably using MOSFETs, but I'll look at other options). If a level shifting circuit with a large "virtual" logic high threshold (say 5V-12V or even more) can be made, that should mean a much higher pull-up value can be used without compromising total noise immunity, since there's much more noise margin there. Is this a dumb/nonsensical idea? (All of this is an exercise in overengineering, I know.)

[David Hess]

That makes sense.

Two other things which can be done to lower power and increase noise immunity is to replace the pull-up with a current source and add an RC snubber across the transmission line to limit bandwidth.  The RC snubber may just be a suitably sized capacitor.

[eddie1]

Thanks! I'm not sure what a current source as a replacement for a pull-up resistor would be in this context (I'll have to do some more reading on this), but the addition of a capacitor sounds like a great idea I hadn't considered. Overall, for this application where the pull-up can be to 12V, it sounds like that's the best overall option: it reduces the load on the point-of-load regulator and seems likely to allow for a more robust design at lower power.

I'll have to figure out a way to test this (maybe a shielded box with a noise-generating circuit that I can then put the target circuit in and watch with oscilloscope probes?), but from what I understand, external noise causing spurious inputs isn't really a theoretical problem that only occurs in an extreme case like nearby high-voltage AC or something. MCUs tend to have weak pull-ups (anywhere between 30k and 100k in the MCUs I've looked at, and usually with really poor tolerance) and I have come across forum posts reporting spurious inputs that were resolved by switching to a stronger (external) pull-up. I think that means I should be able to come up with a suitable testing environment.

(I'm approaching each part of this as a learning opportunity. The overthinking and overengineering on a non-critical hobby project is intentional.)