So for example something like this.
I wasn't able to find a spice model of a binary counter (and didn't care to search beyond a couple of models I readily remembered), so it's not shown, but that part is trivial -- just look in the datasheets. Suitable parts would be for example HEF4520, CD4520 or similar. A decade counter such as CD4017 will also work -- we only need to count to 2.
I also had no success simulating a D flip-flip frequency divider (aka toggle circuit). Probably the model was wrong, would need more time to figure it out. But that can also be an option, as long as it works.
Now, once you have two signals, one the original one, and another with frequency divided by 2, you do the following. You actually need an AND gate, not NAND (as it outputs an inverted signal), or, as shown, NAND followed by inverter:
The RC delay at the input receiving the original signal is required to fix the glitch of the NAND output going briefly low when the original signal is transitioning to high and the divided one to low: you need to hold the original signal low for a bit longer. The RC values are to be determined experimentally.
Since one of the NAND inputs will receive a signal that may not have sufficiently short rise and fall times because of the RC delay, it has to be one that has Schmitt trigger inputs, such as the 74xxxxx132 gates, for example. See e.g.
https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits to find suitable parts that will be available wherever you'll be sourcing them from.
p.s. this also preserves the original pulse width, save for the small length change caused by the RC delay circuit. What is the frequency of your signal?